EDSCR
External Debug Status and Control Register
EDSCR is in the Core power domain
Debug
0x088
EDSCR
When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus()
ERROR
When SoftwareLockStatus(addrdesc)
RO
RW
MDSCR_EL1
Architectural
AArch64
31
6
31
6
31
29
27
26
23
21
19
19
14
14
6
6
31
29
27
26
23
21
19
19
14
14
6
6
when FEAT_AA64 is implemented
DBGDSCRext
Architectural
AArch32
31
6
31
6
31
29
27
26
23
21
19
19
14
14
6
6
31
29
27
26
23
21
19
19
14
14
6
6
MDCCSR_EL0
Architectural
AArch64
30
29
30
29
30
29
30
29
when FEAT_AA64 is implemented
DBGDSCRint
Architectural
AArch32
30
29
30
29
30
29
30
29
Main control register for the debug implementation.
Debug
EDSCR is a 32-bit register.
TFO
31
31
0
Trace Filter Override. Overrides the Trace Filter controls allowing the external debugger to trace any visible Exception level.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
This bit is ignored by the PE when any of the following is true:
ExternalSecureNoninvasiveDebugEnabled() is FALSE and the Effective value of MDCR_EL3.STE is 1.
FEAT_RME is implemented, ExternalRealmNoninvasiveDebugEnabled() is FALSE, and the Effective value of MDCR_EL3.RLTE is 1.
0b0
Trace Filter controls are not affected.
0b1
Trace Filter controls in TRFCR_EL1 and TRFCR_EL2 are ignored.
Trace Filter controls TRFCR and HTRFCR are ignored.
'0'
When FEAT_TRF is implemented
31
31
31
Reserved, RES0.
Otherwise
RXfull
30
30
30
DTRRX full.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
'0'
RO
TXfull
29
29
29
DTRTX full.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
'0'
RO
ITO
28
28
28
ITR overrun. Set to 0 on entry to Debug state.
When the PE is in Non-debug state
UNKNOWN/WI
RO
RXO
27
27
27
DTRRX overrun.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
'0'
RO
TXU
26
26
26
DTRTX underrun.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
'0'
RO
PipeAdv
25
25
25
Pipeline Advance. Indicates that software execution is progressing.
The architecture does not define precisely when this field is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing. For example, a PE might set this field to 1 each time the PE retires one or more instructions, or at periodic intervals during the progression of an instruction.
When FEAT_MOPS is implemented, CPY, CPYF, SET, and SETG are examples of instructions that periodically make forward progress.
0b0
No progress has been made by the PE since the last time this field was cleared to zero by writing 1 to EDRCR.CSPA.
0b1
Progress has been made by the PE since the last time this field was cleared to zero by writing 1 to EDRCR.CSPA.
AU
RO
ITE
24
24
24
ITR empty.
When the PE is in Non-debug state
UNKNOWN/WI
RO
INTdis
23
22
1:0
Interrupt and SError exception disable. Disables taking interrupts and SError exceptions in Non-debug state.
This control affects both physical and virtual interrupts and SError exceptions.When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the following System registers:
MDSCR_EL1.
DBGDSCRext.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
When FEAT_RME is implemented, bit[23] of this register is RES0.
0b00
This bit has no effect on the masking of interrupts and SError exceptions.
0b01
If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Non-secure state are masked.
If ExternalSecureInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Secure state are masked.
If ExternalRootInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Root state are masked.
If ExternalRealmInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Realm state are masked.
'00'
When FEAT_RME is implemented
INTdis
23
22
1:0
Interrupt and SError exception disable. Disables taking interrupts and SError exceptions in Non-debug state.
This control affects both physical and virtual interrupts and SError exceptions.When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the following System registers:
MDSCR_EL1.
DBGDSCRext.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
When FEAT_Debugv8p4 is implemented, bit[23] of this register is RES0.
0b00
Masking of interrupts and SError exceptions is controlled by PSTATE and interrupt routing controls.
0b01
If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Non-secure state are masked.
If ExternalSecureInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Secure state are masked.
'00'
When FEAT_Debugv8p4 is implemented
INTdis
23
22
1:0
Interrupt and SError exception disable. Disables taking interrupts and SError exceptions in Non-debug state.
This control affects both physical and virtual interrupts and SError exceptions.When OSLSR_EL1.OSLK is 1, this field can be indirectly read and written through the following System registers:
MDSCR_EL1.
DBGDSCRext.
The Effective value of this field is 0b00 when ExternalInvasiveDebugEnabled() is FALSE.
Support for the values 0b01 and 0b10 is IMPLEMENTATION DEFINED. If these values are not supported, they are reserved. If programmed with a reserved value, the PE behaves as if EDSCR.INTdis has been programmed with a defined value, other than for a direct read of EDSCR, and the value returned by a read of EDSCR.INTdis is UNKNOWN.
0b00
Masking of interrupts and SError exceptions is controlled by PSTATE and interrupt routing controls.
0b01
If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Non-secure EL1 are masked.
0b10
If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Non-secure state are masked.
If ExternalSecureInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Secure EL1 are masked.
0b11
If ExternalInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Non-secure state are masked.
If ExternalSecureInvasiveDebugEnabled() is TRUE, then all interrupts and SError exceptions taken to Secure state are masked.
'00'
Otherwise
TDA
21
21
21
Traps accesses to the following debug registers:
AArch64: DBGBCR<n>_EL1, DBGBVR<n>_EL1, DBGWCR<n>_EL1, DBGWVR<n>_EL1.
AArch32: DBGBCR<n>, DBGBVR<n>, DBGBXVR<n>, DBGWCR<n>, DBGWVR<n>.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
0b0
Accesses to debug registers do not generate a Software Access Debug event.
0b1
Accesses to debug registers generate a Software Access Debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed.
'0'
MA
20
20
20
Memory access mode. Controls the use of Memory access mode for accessing ITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.
Possible values of this field are:
0b0
Normal access mode.
0b1
Memory access mode.
'0'
SC2
19
19
0
Sample CONTEXTIDR_EL2. Controls whether the PC Sample-based Profiling Extension samples CONTEXTIDR_EL2 or VTTBR_EL2.VMID.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
0b0
Sample VTTBR_EL2.VMID.
0b1
Sample CONTEXTIDR_EL2.
'0'
When FEAT_PCSRv8 is implemented, EL2 is implemented, FEAT_Debugv8p1 is implemented, and FEAT_PCSRv8p2 is not implemented
19
19
19
Reserved, RES0.
Otherwise
NS
18
18
0
Non-secure status. Together with the NSE field, gives the current Security state:
NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.
When the PE is in Non-debug state
UNKNOWN/WI
RO
When FEAT_RME is implemented
NS
18
18
0
Non-secure status. In Debug state, gives the current Security state:
0b0
Secure state.
0b1
Non-secure state.
When the PE is in Non-debug state
UNKNOWN/WI
RO
Otherwise
17
17
17
Reserved, RES0.
SDD
16
16
0
EL3 debug disabled.
On entry to Debug state:
If entering from EL3, SDD is set to 0.
Otherwise, SDD is set to the inverse of ExternalRootInvasiveDebugEnabled().
In Debug state, the value of SDD does not change, even if ExternalRootInvasiveDebugEnabled() changes.
In Non-debug state, SDD returns the inverse of ExternalRootInvasiveDebugEnabled(), regardless of the current Security state of the PE.
RO
When FEAT_RME is implemented
SDD
16
16
0
Secure debug disabled.
On entry to Debug state:
If entering in Secure state, then SDD is set to 0.
If entering in Non-secure state, then SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled().
In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.
In Non-debug state, SDD returns the inverse of ExternalSecureInvasiveDebugEnabled(), regardless of the current Security state of the PE. If the authentication signals that control ExternalSecureInvasiveDebugEnabled() change, then a context synchronization event is required to guarantee their effect.
RO
When FEAT_Secure is implemented
16
16
16
Reserved, RES1.
Otherwise
NSE
15
15
0
Together with the NS field, this field gives the current Security state.
For a description of the values derived by evaluating NS and NSE together, see EDSCR.NS.
In Non-debug state, this bit is UNKNOWN.
RO
When FEAT_RME is implemented
15
15
15
Reserved, RES0.
Otherwise
HDE
14
14
14
Halting debug enable.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
0b0
Halting disabled for Breakpoint, Watchpoint and Halt Instruction debug events.
0b1
Halting enabled for Breakpoint, Watchpoint and Halt Instruction debug events.
'0'
RW
13
10
13:10
Exception level Execution state status. In Debug state, each bit gives the current Execution state of each Exception level.
0b1111
Any of the following:
The PE is in Non-debug state.
The PE is at EL0 using AArch64.
The PE is not at EL0, and EL1 is using AArch64. If implemented and enabled in the current Security state, EL2 and EL3 are using AArch64.
0b1110
The PE is in Debug state at EL0. EL0 is using AArch32. EL1 is using AArch64. If implemented and enabled in the current Security state, EL2 and EL3 are using AArch64.
When FEAT_AA32 is implemented
0b110x
The PE is in Debug state. EL0 and EL1 are using AArch32. EL2 is enabled in the current Security state and is using AArch64. If implemented, EL3 is using AArch64.
When FEAT_AA32 is implemented and EL2 is implemented
0b10xx
The PE is in Debug state. EL0 and EL1 are using AArch32. EL2 is not implemented, disabled in the current Security state, or using AArch32. EL3 is using AArch64.
When FEAT_AA32 is implemented and EL3 is implemented
0b0xxx
The PE is in Debug state. All Exception levels are using AArch32.
When FEAT_AA32 is implemented
When the PE is in Non-debug state
RAO/WI
RO
EL
9
8
9:8
Exception level. In Debug state, gives the current Exception level of the PE.
When the PE is in Non-debug state
RAZ/WI
RO
A
7
7
7
SError exception pending. In Debug state, indicates whether an SError exception is pending:
If EL2 is enabled in the current Security state, the PE is executing at EL0 or EL1, HCR_EL2.TGE is 0 and either HCR_EL2.AMO is 1 or FEAT_DoubleFault2 is implemented and the Effective value of HCRX_EL2.TMEA is 1, a virtual SError exception.
Otherwise, if FEAT_E3DSE is implemented, the PE is executing at EL0, EL1, or EL2, and SCR_EL3.EnDSE is 1, a delegated SError exception.
Otherwise, a physical SError exception.
A debugger can read EDSCR to check whether an SError exception is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.
0b0
No SError exception pending.
0b1
SError exception pending.
When the PE is in Non-debug state
UNKNOWN/WI
RO
ERR
6
6
6
Cumulative error flag. This bit is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
When OSLSR_EL1.OSLK is 1, this bit can be indirectly read and written through MDSCR_EL1 and DBGDSCRext.
'0'
RO
STATUS
5
0
5:0
On entering Debug state, the PE sets this field to indicate the reason for halting.
All other values are reserved.
The PE resets into Non-debug state. However, if the PE enters Debug state immediately after reset, then the reset value is overwritten with the reason for halting.
0b000001
PE is restarting, exiting Debug state.
0b000010
PE is in Non-debug state.
0b000111
Breakpoint.
0b010011
External debug request.
0b011011
Halting step, normal.
0b011111
Halting step, exclusive.
0b100011
OS Unlock Catch.
0b100111
Reset Catch.
0b101011
Watchpoint.
0b101111
HLT instruction.
0b110011
Software access to debug register.
0b110111
Exception Catch.
0b111011
Halting step, no syndrome.
'000010'
RO
2026-03-26 20:27:25
2026-03_rel