EDSCR2 External Debug Status and Control Register 2 EDSCR2 is in the Core power domain when FEAT_Debugv8p9 is implemented or FEAT_TRBE_EXT is implemented Debug 0x028 EDSCR2 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR RW MDSCR_EL1 Architectural AArch64 3 1 35 33 3 3 1 1 35 35 33 33 Main control register 2 for the debug implementation. Debug EDSCR2 is a 32-bit register. 31 4 31:4 Reserved, RES0. EHBWE 3 3 0 Extended Halting Breakpoint and Watchpoint Enable. Enables use of additional breakpoints or watchpoints. When OSLSR_EL1.OSLK is 1, this field can be read and written through the MDSCR_EL1 System register. It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI. 0b0 Halting disabled for Breakpoint and Watchpoint debug events generated by each breakpoint <n> and Watchpoint <n>, where n is greater than or equal to 16. 0b1 Breakpoints and Watchpoint debug events are not affected by this mechanism. '0' When FEAT_Debugv8p9 is implemented 3 3 3 Reserved, RES0. Otherwise 2 2 2 Reserved, RES0. TTA 1 1 0 Trap Trace Accesses. Traps access to the following System registers: AArch64: TRBBASER_EL1, TRBIDR_EL1, TRBLIMITR_EL1, TRBMAR_EL1, TRBMPAM_EL1, TRBPTR_EL1, TRBSR_EL1, TRBTRG_EL1, TRCACATR<n>, TRCACVR<n>, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVR<n>, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLR<n>, TRCCNTRLDVR<n>, TRCCNTVR<n>, TRCCONFIGR, TRCDEVARCH, TRCDEVID, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR<n>, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPEC<n>, TRCITEEDCR, TRCOSLSR, TRCPRGCTLR, TRCQCTLR, TRCRSCTLR<n>, TRCRSR, TRCSEQEVR<n>, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCR<n>, TRCSSCSR<n>, TRCSSPCICR<n>, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1, and TRCVMIDCVR<n>. When OSLSR_EL1.OSLK is 1, this field can be read and written through the MDSCR_EL1 System register. 0b0 Accesses to trace System registers do not generate a Software Access debug event. 0b1 Accesses to trace System registers generate a Software Access debug event, if OSLSR_EL1.OSLK is 0 and if halting is allowed. '0' When FEAT_TRBE_EXT is implemented or FEAT_ETEv1p3 is implemented 1 1 1 Reserved, RES0. Otherwise 0 0 0 Reserved, RES0. 2026-03-26 20:27:25 2026-03_rel