EDVIDSR External Debug Virtual Context Sample Register EDVIDSR is in the Core power domain when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented Debug 0x0A8 EDVIDSR When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() ERROR RO Contains sampled values captured on reading EDPCSR[31:0]. Debug If FEAT_Debugv8p1 is implemented, the format of this register differs depending on the value of EDSCR.SC2. Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented in the external debug registers space. When FEAT_PCSRv8 is implemented in the external debug registers space, if EL2 is not implemented and EL3 is not implemented, it is IMPLEMENTATION DEFINED whether EDVIDSR is implemented. FEAT_PCSRv8p2 implements the FEAT_PCSRv8 in the Performance Monitors registers space. EDVIDSR is a 32-bit register. When FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == '0' FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == 0 This format applies in all Armv8.0 implementations. NS 31 31 31 Non-secure state sample. Indicates the Security state associated with the most recent EDPCSR sample. If EL3 is not implemented, this bit indicates the Effective value of SCR.NS. 0b0 Sample is from Secure state. 0b1 Sample is from Non-secure state. AU E2 30 30 0 Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. 0b0 Sample is not from EL2. 0b1 Sample is from EL2. AU When EL2 is implemented 30 30 30 Reserved, RES0. Otherwise E3 29 29 0 Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with EL3 using AArch64. 0b0 Sample is not from EL3 using AArch64. 0b1 Sample is from EL3 using AArch64. AU When EL3 is implemented and FEAT_AA64 is implemented 29 29 29 Reserved, RES0. Otherwise HV 28 28 28 EDPCSRhi (EDPCSR[63:32]) valid. Indicates whether bits [63:32] of the most recent EDPCSR sample might be nonzero: An EDVIDSR.HV value of 1 does not mean that the value of EDPCSRhi is nonzero. An EDVIDSR.HV value of 0 is a hint that EDPCSRhi (EDPCSR[63:32]) does not need to be read. 0b0 Bits[63:32] of the most recent EDPCSR sample are zero. 0b1 Bits[63:32] of the most recent EDPCSR sample might be nonzero. AU 27 16 27:16 Reserved, RES0. VMID[15:8] 15 8 7:0 Extension to VMID[7:0]. For more information, see VMID[7:0]. AU When FEAT_VMID16 is implemented and EL2 is implemented 15 8 15:8 Reserved, RES0. Otherwise VMID 7 0 7:0 VMID sample. The VMID associated with the most recent EDPCSRlo (EDPCSR[31:0]) sample. When the most recent EDPCSR sample was generated: This field is RES0 if any of the following apply: The PE is executing in Secure state. The PE is executing at EL2. Otherwise: If EL2 is using AArch64 and either FEAT_VMID16 is not implemented or VTCR_EL2.VS is 1, this field is set to VTTBR_EL2.VMID. If EL2 is using AArch64, FEAT_VMID16 is implemented, and VTCR_EL2.VS is 0, PMVIDSR.VMID[7:0] is set to VTTBR_EL2.VMID[7:0] and PMVIDSR.VMID[15:8] is RES0. If EL2 is using AArch32, this field is set to VTTBR.VMID. AU When EL2 is implemented 7 0 7:0 Reserved, RES0. Otherwise When EL2 is implemented, FEAT_Debugv8p1 is implemented, and EDSCR.SC2 == '1' EL2 is implemented, FEAT_Debugv8p1 is implemented, and EDSCR.SC2 == 1 CONTEXTIDR_EL2 31 0 31:0 Context ID. The value of CONTEXTIDR_EL2 that is associated with the most recent EDPCSR sample. When the most recent EDPCSR sample is generated: If the PE is not executing at EL3, EL2 is using AArch64, and EL2 is enabled in the current Security state, then this field is set to the Context ID sampled from CONTEXTIDR_EL2. Otherwise, this field is set to an UNKNOWN value. AU When FEAT_Debugv8p1 is not implemented or EDSCR.SC2 == '0' When EL2 is implemented, FEAT_Debugv8p1 is implemented, and EDSCR.SC2 == '1' IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'. 2026-03-26 20:27:25 2026-03_rel