<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>EDWAR</reg_short_name>
        
        <reg_long_name>External Debug Watchpoint Address Register</reg_long_name>

        <power_domain_text>EDWAR is in the Core power domain</power_domain_text>


      
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>Debug</reg_component>
    <reg_offset><hexnumber>0x030</hexnumber></reg_offset>
    <reg_instance>EDWAR</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Returns the virtual data address being accessed when a Watchpoint Debug Event was triggered.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Debug</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>The value of this register is <arm-defined-word>UNKNOWN</arm-defined-word> if the PE is in Non-debug state, or if <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.STATUS is not <binarynumber>0b101011</binarynumber>.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>EDWAR is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ADDR</field_name>
    <field_shortdesc>Watchpoint address</field_shortdesc>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before"><para>Watchpoint address. The data virtual address being accessed when a Watchpoint Debug Event was triggered and caused entry to Debug state. This address must be within a naturally-aligned block of memory of power-of-two size no larger than the <register_link id="AArch64-dc-zva.xml" state="AArch64">DC ZVA</register_link> block size.</para>
<para>The value of this register is <arm-defined-word>UNKNOWN</arm-defined-word> if the PE is in Non-debug state, or if Debug state was entered other than for a Watchpoint debug event.</para>
<para>The value of EDWAR[63:32] is <arm-defined-word>UNKNOWN</arm-defined-word> if Debug state was entered for a Watchpoint debug event taken from AArch32 state.</para>
<para>The EDWAR is subject to the same alignment rules as the reporting of a watchpointed address in the FAR. See <xref linkend="#BCGCFDCG">'Exception syndrome information and preferred return address'</xref>.</para></field_description>
    <field_resets>
      <field_reset reset_type="Cold">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" msb="63" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>