ERRACR Access Configuration Register when (FEAT_RME is implemented or HaveSecureState()) and FEAT_RASSA_ACR is implemented RAS 0xE40 ERRACR When (FEAT_RME is implemented and an access is not Root) or an access is Non-secure RAZ/WI RW Controls visibility of error records. RAS ERRACR is a 64-bit register. IMPLEMENTATION DEFINED 63 32 63:32 IMPLEMENTATION DEFINED observation controls. Additional IMPLEMENTATION DEFINED access control bits. IMPL 31 31 31 0b1 Indicates ERRACR is present. RAO/WI 30 6 30:6 Reserved, RES0. RLRA 5 4 1:0 Realm Restricted Access. Controls Realm access to error records and interrupt configuration registers in the error record group. All other values are reserved. This control applies to all error record registers (ERR<n>*, including fault injection registers ERR<n>PFG* if implemented), and interrupt configuration registers (ERR<irq>CR<m> and ERRIRQSR, if implemented) in the error record group. The effect on any IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. When Realm access to error records is disabled, a Realm read of ERRGSR<m> will return the error record status for the error records that cannot be accessed. When Realm access is fully or partially disabled, the effect on Realm accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. The reset domain and value of this field is IMPLEMENTATION DEFINED, and depends on the security policy of the component implementing this register. 0b00 Realm access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Realm accesses. 0b01 Realm read access is enabled. Realm writes are ignored. 0b11 Realm read/write access is allowed. If the error record group supports MSIs, generated MSIs are always Non-secure. ID ID When FEAT_RME is implemented and the error record group allows configuration of Secure and Realm register accesses 5 4 5:4 Reserved, RAZ/WI. Otherwise SRA 3 2 1:0 Secure Restricted Access. Controls Secure access to error records and interrupt configuration registers in the error record group. All other values are reserved. This control applies to all error record registers (ERR<n>*, including fault injection registers ERR<n>PFG* if implemented), and interrupt configuration registers (ERR<irq>CR<m> and ERRIRQSR, if implemented) in the error record group. The effect on any IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. When Secure access to error records is disabled, a Secure read of ERRGSR<m> will return the error record status for the error records that cannot be accessed. When Secure access is fully or partially disabled, the effect on Secure accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. The reset domain and value of this field is IMPLEMENTATION DEFINED, and depends on the security policy of the component implementing this register. 0b00 Secure access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Secure accesses. 0b01 Secure read access is enabled. Secure writes are ignored. 0b11 Secure read/write access is allowed. ID ID When HaveSecureState(), FEAT_RME is implemented, and the error record group allows configuration of Secure and Realm register accesses 3 2 3:2 Reserved, RAZ/WI. Otherwise NSRA 1 0 1:0 Non-secure Restricted Access. Controls Non-secure access to error records and interrupt configuration registers in the error record group. All other values are reserved. This control applies to all error record registers (ERR<n>*, including fault injection registers ERR<n>PFG* if implemented), and interrupt configuration registers (ERR<irq>CR<m> and ERRIRQSR, if implemented) in the error record group. The effect on any IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. When Non-secure access to error records is disabled, a Non-secure read of ERRGSR<m> will return the error record status for the error records that cannot be accessed. When Non-secure access is fully or partially disabled, the effect on Non-secure accesses to IMPLEMENTATION DEFINED registers is IMPLEMENTATION DEFINED. If FEAT_RME is implemented and ERRACR.{RLRA, SRA} are not implemented, then ERRACR.NSRA applies to all Security states other than Root. The reset domain and value of this field is IMPLEMENTATION DEFINED, and depends on the security policy of the component implementing this register. 0b00 Non-secure access is disabled. All error record, ERR<irq>CR<m>, and ERRIRQSR registers are RAZ/WI to Non-secure accesses. 0b01 Non-secure read access is enabled. Non-secure writes are ignored. 0b11 Non-secure read/write access is allowed. If the error record group supports MSIs, generated MSIs are always Non-secure. ID ID This section shows the offset of ERRACR when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRACR. 2026-03-26 20:27:25 2026-03_rel