ERRCRICR2 Critical Error Interrupt Configuration Register 2 when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR registers) and interrupt configuration registers are implemented RAS 0xEAC ERRCRICR2 When the implementation uses message-signaled interrupts, (an access is Non-secure or an access is Realm), the implementation uses the recommended layout for the ERRIRQCR registers, and ERRCRICR2.NSMSI configures the physical address space for message-signaled interrupts as Secure RO RW Critical Error Interrupt control and configuration register. RAS ERRCRICR2 is implemented only as part of a memory-mapped group of error records. ERRCRICR2 is a 32-bit register. When the Critical Error Interrupt is implemented, the implementation uses the recommended layout for the ERRIRQCR registers, and the implementation uses simple interrupts Critical Error Interrupt is implemented, recommended layout for simple interrupts 31 8 31:8 Reserved, RES0. IRQEN 7 7 7 Interrupts enable. Enables generation of interrupts. 0b0 Disabled. 0b1 Enabled. ID 6 0 6:0 Reserved, RES0. When the implementation uses message-signaled interrupts, the Critical Error Interrupt is implemented, and the implementation uses the recommended layout for the ERRIRQCR registers Critical Error Interrupt is implemented, recommended layout for message-signaled interrupts 31 8 31:8 Reserved, RES0. IRQEN 7 7 0 Message signaled interrupt enable. Enables generation of message signaled interrupts. 0b0 Disabled. 0b1 Enabled. '0' When the component supports disabling message signaled interrupts 7 7 0 Reserved, RES0. Message signaled interrupts are always enabled. Otherwise NSMSI 6 6 0 Non-secure message signaled interrupt. Defines the physical address space for message signaled interrupts. 0b0 Secure physical address space. 0b1 Non-secure physical address space. ID When an access is Non-secure RO When an access is Realm RO RW When the component supports configuring the physical address space for message signaled interrupts 6 6 0 Reserved, RES0. The physical address space for message signaled interrupts is IMPLEMENTATION DEFINED. Otherwise SH 5 4 1:0 Shareability. Defines the Shareability domain for message signaled interrupts. All other values are reserved. This field is ignored when ERRCRICR2.MemAttr specifies any of the following memory types: Any Device memory type. Normal memory, Inner Non-cacheable, Outer Non-cacheable. All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable. 0b00 Not shared. 0b10 Outer Shareable. 0b11 Inner Shareable. AU When the component supports configuring the Shareability domain for message signaled interrupts 5 4 1:0 Reserved, RES0. The Shareability domain for message signaled interrupts is IMPLEMENTATION DEFINED. Otherwise MemAttr 3 0 3:0 Memory type. Defines the memory type and attributes for message signaled interrupts. All other values are reserved. This is the same format as the VMSAv8-64 stage 2 memory region attributes. 0b0000 Device-nGnRnE memory. 0b0001 Device-nGnRE memory. 0b0010 Device-nGRE memory. 0b0011 Device-GRE memory. 0b0101 Normal memory, Inner Non-cacheable, Outer Non-cacheable. 0b0110 Normal memory, Inner Write-Through, Outer Non-cacheable. 0b0111 Normal memory, Inner Write-Back, Outer Non-cacheable. 0b1001 Normal memory, Inner Non-cacheable, Outer Write-Through. 0b1010 Normal memory, Inner Write-Through, Outer Write-Through. 0b1011 Normal memory, Inner Write-Back, Outer Write-Through. 0b1101 Normal memory, Inner Non-cacheable, Outer Write-Back. 0b1110 Normal memory, Inner Write-Through, Outer Write-Back. 0b1111 Normal memory, Inner Write-Back, Outer Write-Back. AU When the component supports configuring the memory type for message signaled interrupts 3 0 3:0 Reserved, RES0. The memory type used for message signaled interrupts is IMPLEMENTATION DEFINED. Otherwise When the implementation does not use the recommended layout for the ERRIRQCR registers IMPLEMENTATION DEFINED layout IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. When the Critical Error Interrupt is implemented, the implementation uses the recommended layout for the ERRIRQCR registers, and the implementation uses simple interrupts When the implementation uses message-signaled interrupts, the Critical Error Interrupt is implemented, and the implementation uses the recommended layout for the ERRIRQCR registers When the implementation does not use the recommended layout for the ERRIRQCR registers If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRCRICR2 are IMPLEMENTATION DEFINED. This section shows the offset of ERRCRICR2 when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRCRICR2. 2026-03-26 20:27:25 2026-03_rel