ERRDEVARCH Device Architecture Register RAS 0xFBC ERRDEVARCH RO Provides discovery information for the component. RAS ERRDEVARCH is implemented only as part of a memory-mapped group of error records. ERRDEVARCH is a 32-bit register. ARCHITECT 31 21 31:21 Defines the architect of the component. For RAS, this is Arm Limited. Bits [31:28] are the JEP106 continuation code, 0b0100. Bits [27:21] are the JEP106 identification code, 0b0111011. Reads as 0b01000111011. RO PRESENT 20 20 20 DEVARCH present. Indicates that the ERRDEVARCH register is present. Reads as 0b1. RO REVISION 19 16 3:0 Revision. Defines the architecture revision of the component. All other values are reserved. 0b0000 RAS System Architecture, error record group v1.0. 0b0001 RAS System Architecture, error record group v1.1. As 0b0000 and also: Simplifies ERR<n>STATUS. Adds support for additional ERR<n>MISC<m> registers. Adds support for the optional RAS Timestamp Extension. Adds support for the optional Common Fault Injection Model Extension. RO When UInt(ERRDEVARCH.ARCHPART) == 0xA00 and ERRDEVARCH.ARCHVER == '0000' REVISION 19 16 3:0 Revision. Defines the architecture revision of the component. All other values are reserved. 0b0000 RAS System Architecture, error record group v2.0. RO When UInt(ERRDEVARCH.ARCHPART) == 0xA00 and ERRDEVARCH.ARCHVER == '0001' REVISION 19 16 3:0 Revision. Defines the architecture revision of the component. All other values are reserved. 0b0000 RAS System Architecture, fault injection group v1.0. RO When UInt(ERRDEVARCH.ARCHPART) == 0xA08 and ERRDEVARCH.ARCHVER == '0000' 19 16 19:16 Reserved, RES0. Otherwise ARCHVER 15 12 3:0 Architecture Version. Defines the architecture version of the component. All other values are reserved. ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHVER is ERRDEVARCH.ARCHID[15:12]. 0b0000 RAS System Architecture, error record group v1. 0b0001 RAS System Architecture, error record group v2. As 0b0000 and also: Adds an optional access control register, ERRACR. Adds an optional control for disabling error counters. Adds optional fault handling interrupt controls for Deferred errors. Adds support for continuation and proxy error records. Adds support for implementing Common Fault Injection Mechanism registers in a separate page from the error record registers. Adds support for simple interrupt configuration registers. Defines fields in ERRDEVID that describe these properties. RO When UInt(ERRDEVARCH.ARCHPART) == 0xA00 ARCHVER 15 12 3:0 Architecture Version. Defines the architecture version of the component. All other values are reserved. ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHVER is ERRDEVARCH.ARCHID[15:12]. 0b0000 RAS System Architecture, fault injection group v1. RO When UInt(ERRDEVARCH.ARCHPART) == 0xA08 15 12 15:12 Reserved, RES0. Otherwise ARCHPART 11 0 11:0 Architecture Part. Defines the architecture of the component. ERRDEVARCH.ARCHVER and ERRDEVARCH.ARCHPART are also defined as a single field, ERRDEVARCH.ARCHID, so that ERRDEVARCH.ARCHPART is ERRDEVARCH.ARCHID[11:0]. 0xA00 RAS System Architecture, error record group. 0xA08 RAS System Architecture, fault injection group. RO This section shows the offset of ERRDEVARCH when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRDEVARCH. 2026-03-26 20:27:25 2026-03_rel