ERRERICR0 Error Recovery Interrupt Configuration Register 0 when (the Error Recovery Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR registers) and interrupt configuration registers are implemented RAS 0xE90 ERRERICR0 When the implementation uses message-signaled interrupts, (an access is Non-secure or an access is Realm), the implementation uses the recommended layout for the ERRIRQCR registers, and ERRERICR2.NSMSI configures the physical address space for message-signaled interrupts as Secure RO RW Error Recovery Interrupt configuration register. RAS ERRERICR0 is implemented only as part of a memory-mapped group of error records. ERRERICR0 is a 64-bit register. When the Error Recovery Interrupt is implemented, the implementation uses the recommended layout for the ERRIRQCR registers, and the implementation uses simple interrupts Error Recovery Interrupt is implemented, recommended layout for simple interrupts 63 0 63:0 Reserved, RES0. When the implementation uses message-signaled interrupts, the Error Recovery Interrupt is implemented, and the implementation uses the recommended layout for the ERRIRQCR registers Error Recovery Interrupt is implemented, recommended layout for message-signaled interrupts 63 56 63:56 Reserved, RES0. ADDR 55 2 55:2 Message Signaled Interrupt address. (ERRERICR0.ADDR << 2) is the address that the component writes to when signaling the Error Recovery Interrupt. Bits [1:0] of the address are always zero. The physical address size supported by the component is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0. AU 1 0 1:0 Reserved, RES0. When the implementation does not use the recommended layout for the ERRIRQCR registers IMPLEMENTATION DEFINED layout IMPLEMENTATION DEFINED 63 0 63:0 IMPLEMENTATION DEFINED. When the Error Recovery Interrupt is implemented, the implementation uses the recommended layout for the ERRIRQCR registers, and the implementation uses simple interrupts When the implementation uses message-signaled interrupts, the Error Recovery Interrupt is implemented, and the implementation uses the recommended layout for the ERRIRQCR registers When the implementation does not use the recommended layout for the ERRIRQCR registers If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRERICR0 are IMPLEMENTATION DEFINED. This section shows the offset of ERRERICR0 when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRERICR0. 2026-03-26 20:27:25 2026-03_rel