ERRIIDR Implementation Identification Register when RAS System Architecture v1p1 is implemented RAS 0xE10 ERRIIDR RO Defines the implementer of the component. RAS ERRIIDR is a 32-bit register. ProductID 31 20 31:20 Part number, bits [11:0]. The part number is selected by the designer of the component. If ERRPIDR0 and ERRPIDR1 are implemented, ERRPIDR0.PART_0 matches bits [7:0] of ERRIIDR.ProductID and ERRPIDR1.PART_1 matches bits [11:8] of ERRIIDR.ProductID. This field has an IMPLEMENTATION DEFINED value. RO Variant 19 16 19:16 Component major revision. This field distinguishes product variants or major revisions of the product. If ERRPIDR2 is implemented, ERRPIDR2.REVISION matches ERRIIDR.Variant. This field has an IMPLEMENTATION DEFINED value. RO Revision 15 12 15:12 Component minor revision. This field distinguishes minor revisions of the product. If ERRPIDR3 is implemented, ERRPIDR3.REVAND matches ERRIIDR.Revision. This field has an IMPLEMENTATION DEFINED value. RO Implementer 11 0 11:0 Contains the JEP106 manufacturer's identification code of the designer of the RAS component. The code identifies the designer of the component, which might not be the same as the implementer of the device containing the component. Zero is not a valid JEP106 identification code, meaning a value of zero for ERRIIDR indicates this register is not implemented. For an implementation designed by Arm, this field reads as 0x43B. Bits [11:8] contain the JEP106 bank identifier of the designer minus 1. Bit 7 is RES0. Bits [6:0] contain bits [6:0] of the JEP106 manufacturer's identification code of the designer. If ERRPIDR4 is implemented, ERRPIDR4.DES_2 matches bits [11:8] of this field. If ERRPIDR2 is implemented, ERRPIDR2.DES_1 matches bits [6:4] of this field. If ERRPIDR1 is implemented, ERRPIDR1.DES_0 matches bits [3:0] of this field. This field has an IMPLEMENTATION DEFINED value. RO This section shows the offset of ERRIIDR when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRIIDR. 2026-03-26 20:27:25 2026-03_rel