ERRIRQCR<m> Generic Error Interrupt Configuration Register <m> when the interrupt configuration registers are implemented 0 15 RAS 0xE80 + (8 * m) ERRIRQCR<m> RW The ERRIRQCR<m> registers are reserved for IMPLEMENTATION DEFINED interrupt configuration registers. The architecture provides a recommended layout for the ERRIRQCR<m> registers. These registers are named: ERRFHICR0, ERRFHICR1, and ERRFHICR2 for the fault handling interrupt controls. ERRERICR0, ERRERICR1, and ERRERICR2 for the error recovery interrupt controls. ERRCRICR0, ERRCRICR1, and ERRCRICR2 for the critical error interrupt controls. ERRIRQSR for the status register. This section describes the generic, IMPLEMENTATION DEFINED, format. RAS ERRIRQCR<m> is implemented only as part of a memory-mapped group of error records. ERRIRQCR<m> is a 64-bit register. IMPLEMENTATION DEFINED 63 0 63:0 IMPLEMENTATION DEFINED controls. The content of these registers is IMPLEMENTATION DEFINED. This section shows the offset of ERRIRQCR<m> when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRIRQCR<m>. 2026-03-26 20:27:25 2026-03_rel