ERRIRQSR Error Interrupt Status Register when interrupt configuration registers are implemented RAS 0xEF8 ERRIRQSR When the implementation uses message-signaled interrupts, (an access is Non-secure or an access is Realm), the implementation uses the recommended layout for the ERRIRQCR registers, and ERRIRQSR.NSMSI configures the physical address space for message-signaled interrupts as Secure RO RW Interrupt status register. RAS ERRIRQSR is implemented only as part of a memory-mapped group of error records. ERRIRQSR is a 64-bit register. When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts recommended layout for simple interrupts 63 0 63:0 Reserved, RES0. To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers. When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers recommended layout for message-signaled interrupts 63 6 63:6 Reserved, RES0. CRIERR 5 5 0 Critical Error Interrupt Error. 0b0 Critical Error Interrupt write has not returned an error since this field was last cleared to zero. 0b1 Critical Error Interrupt write has returned an error since this field was last cleared to zero. AU W1C When the Critical Error Interrupt is implemented 5 5 5 Reserved, RES0. Otherwise CRI 4 4 0 Critical Error Interrupt write in progress. Software must not disable an interrupt whilst the write is in progress. This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers. 0b0 Critical Error Interrupt write not in progress. 0b1 Critical Error Interrupt write in progress. RO When the Critical Error Interrupt is implemented 4 4 4 Reserved, RES0. Otherwise ERIERR 3 3 0 Error Recovery Interrupt Error. 0b0 Error Recovery Interrupt write has not returned an error since this field was last cleared to zero. 0b1 Error Recovery Interrupt write has returned an error since this field was last cleared to zero. AU W1C When the Error Recovery Interrupt is implemented 3 3 3 Reserved, RES0. Otherwise ERI 2 2 0 Error Recovery Interrupt write in progress. Software must not disable an interrupt whilst the write is in progress. This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers. 0b0 Error Recovery Interrupt write not in progress. 0b1 Error Recovery Interrupt write in progress. RO When the Error Recovery Interrupt is implemented 2 2 2 Reserved, RES0. Otherwise FHIERR 1 1 0 Fault Handling Interrupt Error. 0b0 Fault Handling Interrupt write has not returned an error since this field was last cleared to zero. 0b1 Fault Handling Interrupt write has returned an error since this field was last cleared to zero. AU W1C When the Fault Handling Interrupt is implemented 1 1 1 Reserved, RES0. Otherwise FHI 0 0 0 Fault Handling Interrupt write in progress. Software must not disable an interrupt whilst the write is in progress. This field does not indicate whether an interrupt is active, but rather whether a write triggered by the interrupt is in progress.To determine whether an interrupt is active, software must examine the individual ERR<n>STATUS registers. 0b0 Fault Handling Interrupt write not in progress. 0b1 Fault Handling Interrupt write in progress. RO When the Fault Handling Interrupt is implemented 0 0 0 Reserved, RES0. Otherwise When the implementation does not use the recommended layout for the ERRIRQCR registers IMPLEMENTATION DEFINED layout IMPLEMENTATION DEFINED 63 0 63:0 IMPLEMENTATION DEFINED. When the implementation uses the recommended layout for the ERRIRQCR registers and the implementation uses simple interrupts When the implementation uses message-signaled interrupts and the implementation uses the recommended layout for the ERRIRQCR registers When the implementation does not use the recommended layout for the ERRIRQCR registers If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRIRQSR are IMPLEMENTATION DEFINED. This section shows the offset of ERRIRQSR when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRIRQSR. 2026-03-26 20:27:25 2026-03_rel