ERR<n>ADDR Error Record <n> Address Register when error record n is implemented and error record n includes an address associated with an error 0 65534 RAS 0x018 + (64 * n) ERR<n>ADDR When ERR<n>STATUS.AV == '0', the node that owns error record n implements the Common Fault Injection Model Extension, and ERRPFGF[FirstRecordOfNode(n)].AV == '1' RW When ERR<n>STATUS.AV == '0' UNKNOWN/WI RO or RW If an address is associated with a detected error, then it is written to ERR<n>ADDR when the error is recorded. It is IMPLEMENTATION DEFINED how the recorded address maps to the software-visible physical address. Software might have to reconstruct the actual physical addresses using the identity of the node and knowledge of the system. RAS ERRFR[FirstRecordOfNode(n)] describes the features implemented by the node that owns error record <n>. FirstRecordOfNode(n) is the index of the first error record owned by the same node as error record <n>. If the node owns a single record then FirstRecordOfNode(n) = n. ERR<n>ADDR is a 64-bit register. NS 63 63 0 Non-secure attribute. With ERR<n>ADDR.NSE, indicates the physical address space of the recorded location. 0b0 When ERR<n>ADDR.NSE == 0: ERR<n>ADDR.PADDR is a Secure address. When ERR<n>ADDR.NSE == 1: ERR<n>ADDR.PADDR is a Root address. 0b1 When ERR<n>ADDR.NSE == 0: ERR<n>ADDR.PADDR is a Non-secure address. When ERR<n>ADDR.NSE == 1: ERR<n>ADDR.PADDR is a Realm address. AU When FEAT_RME is implemented NS 63 63 0 Non-secure attribute. 0b0 ERR<n>ADDR.PADDR is a Secure address. 0b1 ERR<n>ADDR.PADDR is a Non-secure address. AU Otherwise SI 62 62 0 Secure Incorrect. Indicates whether ERR<n>ADDR.{NS, NSE} are valid. It is IMPLEMENTATION DEFINED whether this field is read-only or read/write. 0b0 ERR<n>ADDR.{NS, NSE} are correct. That is, they match the software's view of the physical address space for the recorded location. 0b1 ERR<n>ADDR.{NS, NSE} might not be correct, and might not match the software's view of the physical address space for the recorded location. AU When FEAT_RME is implemented SI 62 62 0 Secure Incorrect. Indicates whether ERR<n>ADDR.NS is valid. It is IMPLEMENTATION DEFINED whether this field is read-only or read/write. 0b0 ERR<n>ADDR.NS is correct. That is, it matches the software's view of the Non-secure attribute for the recorded location. 0b1 ERR<n>ADDR.NS might not be correct, and might not match the software's view of the Non-secure attribute for the recorded location. AU Otherwise AI 61 61 61 Address Incorrect. Indicates whether ERR<n>ADDR.PADDR is a valid physical address that is known to match the software's view of the physical address for the recorded location. It is IMPLEMENTATION DEFINED whether this field is read-only or read/write. 0b0 ERR<n>ADDR.PADDR is a valid physical address. That is, it matches the software's view of the physical address for the recorded location. 0b1 ERR<n>ADDR.PADDR might not be a valid physical address, and might not match the software's view of the physical address for the recorded location. AU VA 60 60 60 Virtual Address. Indicates whether ERR<n>ADDR.PADDR field is a virtual address. No context information is provided for the virtual address. When ERR<n>ADDR.VA is recorded as 1, ERR<n>ADDR.{NS, SI, AI} are recorded as {0, 1, 1} and, if FEAT_RME is implemented, ERR<n>ADDR.NSE is recorded as 0. Support for this field is optional. If this field is not implemented and ERR<n>ADDR.PADDR field is a virtual address, then ERR<n>ADDR.{NS, SI, AI} read as {0, 1, 1} and, if FEAT_RME is implemented, ERR<n>ADDR.NSE reads as 0. It is IMPLEMENTATION DEFINED whether this field is read-only or read/write. 0b0 ERR<n>ADDR.PADDR is not a virtual address. 0b1 ERR<n>ADDR.PADDR is a virtual address. AU NSE 59 59 0 Physical Address Space. Together with ERR<n>ADDR.NS, indicates the address space for ERR<n>ADDR.PADDR. AU When FEAT_RME is implemented 59 59 59 Reserved, RES0. Otherwise 58 56 58:56 Reserved, RES0. PADDR 55 0 55:0 Physical Address. Address of the recorded location. If the physical address size implemented by this component is smaller than the size of this field, then high-order bits are unimplemented and either RES0 or have a fixed read-only IMPLEMENTATION DEFINED value. Low-order address bits might also be unimplemented and RES0, for example, if the physical address is always aligned to the size of a protection granule. AU 2026-03-26 20:27:25 2026-03_rel