ERR<n>CTLR Error Record <n> Control Register when error record n is implemented and error record n is the first error record in the node 0 65534 RAS 0x008 + (64 * n) ERR<n>CTLR RW The error control register contains enable bits for the node that writes to this record: Enabling error detection and correction. Enabling the critical error, error recovery, and fault handling interrupts. Enabling in-band error response for uncorrected errors. For each bit, if the node does not support the feature, then the bit is RES0. The definition of each record is IMPLEMENTATION DEFINED. RAS ERR<n>FR contains additional information about the node. ERR<n>CTLR is a 64-bit register. IMPLEMENTATION DEFINED 63 32 63:32 Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software. 31 16 31:16 Reserved, RES0. WDFI 15 15 0 Fault handling interrupt for Deferred errors on writes enable, with ERR<n>CTLR.WFI. When enabled by ERR<n>CTLR.{WDFI, WFI}: The fault handling interrupt is generated for errors recorded as Deferred error on writes. If the corresponding fault handling interrupt control for corrected error events, ERR<n>CTLR.WCFI, is not implemented, then the fault handling interrupt is generated for corrected error events on writes. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 When ERR<n>CTLR.WFI == 0, Fault handling interrupt not generated for Deferred errors on writes. When ERR<n>CTLR.WFI == 1, Fault handling interrupt generated for Deferred errors on writes. 0b1 When ERR<n>CTLR.WFI == 0, Fault handling interrupt generated for Deferred errors on writes. When ERR<n>CTLR.WFI == 1, Fault handling interrupt not generated for Deferred errors on writes. AU When RAS System Architecture v2 is implemented and ERR<n>FR.DFI == '11' 15 15 15 Reserved, RES0. Otherwise DFI 14 14 0 Fault handling interrupt for Deferred errors enable, with ERR<n>CTLR.FI. When ERR<n>FR.DFI == 0b10, this control applies to errors on both reads and writes. When enabled by ERR<n>CTLR.{DFI, FI}: The fault handling interrupt is generated for all errors recorded as Deferred error. If the fault handling interrupt control for corrected error events, ERR<n>CTLR.CFI, is not implemented, then the fault handling interrupt is generated for all corrected error events. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 When ERR<n>CTLR.FI == 0, Fault handling interrupt not generated for Deferred errors. When ERR<n>CTLR.FI == 1, Fault handling interrupt generated for Deferred errors. 0b1 When ERR<n>CTLR.FI == 0, Fault handling interrupt generated for Deferred errors. When ERR<n>CTLR.FI == 1, Fault handling interrupt not generated for Deferred errors. AU When RAS System Architecture v2 is implemented and ERR<n>FR.DFI == '10' RDFI 14 14 0 Fault handling interrupt for Deferred errors on reads enable, with ERR<n>CTLR.RFI. When enabled by ERR<n>CTLR.{RDFI, RFI}: The fault handling interrupt is generated for errors recorded as Deferred error on reads. If the corresponding fault handling interrupt control for corrected error events, ERR<n>CTLR.RCFI, is not implemented, then the fault handling interrupt is generated for corrected error events on reads. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 When ERR<n>CTLR.RFI == 0, Fault handling interrupt not generated for Deferred errors on reads. When ERR<n>CTLR.RFI == 1, Fault handling interrupt generated for Deferred errors on reads. 0b1 When ERR<n>CTLR.RFI == 0, Fault handling interrupt generated for Deferred errors on reads. When ERR<n>CTLR.RFI == 1, Fault handling interrupt not generated for Deferred errors on reads. AU When RAS System Architecture v2 is implemented and ERR<n>FR.DFI == '11' 14 14 14 Reserved, RES0. Otherwise CI 13 13 0 Critical error interrupt enable. When enabled, the critical error interrupt is generated for a critical error condition. 0b0 Critical error interrupt not generated for critical errors. Critical errors are treated as Uncontained errors. 0b1 Critical error interrupt generated for critical errors. AU When ERR<n>FR.CI == '10' 13 13 13 Reserved, RES0. Otherwise CED 12 12 0 Disable generation of corrected error events from error counters. See ERR<n>CTLR.CFI for more information on corrected error events. 0b0 Corrected error events are generated by the error counter or counters. 0b1 Corrected error events are generated when a Corrected error is recorded. AU When RAS System Architecture v2 is implemented, ERR<n>FR.CEC != '000', and ERR<n>FR.CED == '1' 12 12 12 Reserved, RES0. Otherwise WDUI 11 11 0 Error recovery interrupt for Deferred errors on writes enable. When enabled, the error recovery interrupt is generated for errors recorded as Deferred error on writes. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt not generated for Deferred errors on writes. 0b1 Error recovery interrupt generated for Deferred errors on writes. AU When ERR<n>FR.DUI == '11' 11 11 11 Reserved, RES0. Otherwise DUI 10 10 0 Error recovery interrupt for Deferred errors enable. When ERR<n>FR.DUI == 0b10, this control applies to errors arising from both reads and writes. When enabled, the error recovery interrupt is generated for all errors recorded as Deferred error. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt not generated for Deferred errors. 0b1 Error recovery interrupt generated for Deferred errors. AU When ERR<n>FR.DUI == '10' RDUI 10 10 0 Error recovery interrupt for Deferred errors on reads enable. When enabled, the error recovery interrupt is generated for errors recorded as Deferred error on reads. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt not generated for Deferred errors on reads. 0b1 Error recovery interrupt generated for Deferred errors on reads. AU When ERR<n>FR.DUI == '11' 10 10 10 Reserved, RES0. Otherwise WCFI 9 9 0 Fault handling interrupt for corrected error events on writes enable. When enabled, the fault handling interrupt is generated for corrected error events on writes. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt not generated for corrected error events on writes. 0b1 Fault handling interrupt generated for corrected error events on writes. AU When ERR<n>FR.CFI == '11' 9 9 9 Reserved, RES0. Otherwise CFI 8 8 0 Fault handling interrupt for corrected error events enable. When ERR<n>FR.CFI == 0b10, this control applies to errors on both reads and writes. When enabled, the fault handling interrupt is generated for all corrected error events. If the node implements a corrected error counter or counters, and either ERR<n>CTLR.CED is not implemented or ERR<n>CTLR.CED is 0, then a corrected error event is defined as follows: A corrected error event occurs when a counter overflows and sets a counter overflow flag to 1. It is UNPREDICTABLE whether a corrected error event occurs when a software write sets a counter overflow flag to 1. It is UNPREDICTABLE whether a corrected error event occurs when a counter overflows and the overflow flag was previously set to 1. Otherwise, a corrected error event occurs when the error record records an error as a Corrected error. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt not generated for corrected error events. 0b1 Fault handling interrupt generated for corrected error events. AU When ERR<n>FR.CFI == '10' RCFI 8 8 0 Fault handling interrupt for corrected error events on reads enable. When enabled, the fault handling interrupt is generated for corrected error events on reads. If the node implements a corrected error counter or counters, and either ERR<n>CTLR.CED is not implemented or ERR<n>CTLR.CED is 0, then a corrected error event is defined as follows: A corrected error event occurs when a counter overflows and sets a counter overflow flag to 1. It is UNPREDICTABLE whether a corrected error event occurs when a software write sets a counter overflow flag to 1. It is UNPREDICTABLE whether a corrected error event occurs when a counter overflows and the overflow flag was previously set to 1. Otherwise, a corrected error event occurs when the error record records an error as a Corrected error. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt not generated for corrected error events on reads. 0b1 Fault handling interrupt generated for corrected error events on reads. AU When ERR<n>FR.CFI == '11' 8 8 8 Reserved, RES0. Otherwise WUE 7 7 0 In-band error response on writes enable. When enabled, responses to writes that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External abort). It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester. 0b0 In-band error response for uncorrected errors on writes disabled. 0b1 In-band error response for uncorrected errors on writes enabled. AU When ERR<n>FR.UE == '11' 7 7 7 Reserved, RES0. Otherwise WFI 6 6 0 Fault handling interrupt on writes enable. When enabled: The fault handling interrupt is generated for errors recorded as Uncorrected error on writes. If the corresponding fault handling interrupt control for Deferred errors, ERR<n>CTLR.WDFI, is not implemented, then the fault handling interrupt is generated for errors recorded as Deferred error on writes. If the corresponding fault handling interrupt controls for Deferred errors and corrected error events, ERR<n>CTLR.{WDFI, WCFI}, are not implemented, then the fault handling interrupt is generated for corrected error events on writes. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt on writes disabled. 0b1 Fault handling interrupt on writes enabled. AU When ERR<n>FR.FI == '11' 6 6 6 Reserved, RES0. Otherwise WUI 5 5 0 Uncorrected error recovery interrupt on writes enable. When enabled, the error recovery interrupt is generated for errors recorded as Uncorrected error on writes. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt on writes disabled. 0b1 Error recovery interrupt on writes enabled. AU When ERR<n>FR.UI == '11' 5 5 5 Reserved, RES0. Otherwise UE 4 4 0 In-band error response enable. When ERR<n>FR.UE == 0b10, this control applies to errors arising from both reads and writes. When enabled, responses to transactions that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External abort). It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester. 0b0 In-band error response for uncorrected errors disabled. 0b1 In-band error response for uncorrected errors enabled. AU When ERR<n>FR.UE == '10' RUE 4 4 0 In-band error response on reads enable. When enabled, responses to reads that detect an error that is not corrected and is not deferred are signaled with an in-band error response (External abort). It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as Deferred error, but is not deferred to the Requester, will signal an in-band error response to the Requester. 0b0 In-band error response for uncorrected errors on reads disabled. 0b1 In-band error response for uncorrected errors on reads enabled. AU When ERR<n>FR.UE == '11' 4 4 4 Reserved, RES0. Otherwise FI 3 3 0 Fault handling interrupt enable. When ERR<n>FR.FI == 0b10, this control applies to errors on both reads and writes. When enabled: The fault handling interrupt is generated for all errors recorded as Uncorrected error. If the fault handling interrupt control for Deferred errors, ERR<n>CTLR.DFI, is not implemented, then the fault handling interrupt is generated for all errors recorded as Deferred error. If the fault handling interrupt controls for Deferred errors and corrected error events, ERR<n>CTLR.{DFI, CFI}, are not implemented, then the fault handling interrupt is generated for all corrected error events. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt disabled. 0b1 Fault handling interrupt enabled. AU When ERR<n>FR.FI == '10' RFI 3 3 0 Fault handling interrupt on reads enable. When enabled: The fault handling interrupt is generated for errors recorded as Uncorrected error on reads. If the corresponding fault handling interrupt control for Deferred errors, ERR<n>CTLR.RDFI, is not implemented, then the fault handling interrupt is generated for errors recorded as Deferred error on reads. If the corresponding fault handling interrupt controls for Deferred errors and corrected error events, ERR<n>CTLR.{RDFI, RCFI}, are not implemented, then the fault handling interrupt is generated for corrected error events on reads. See ERR<n>CTLR.CFI for more information on corrected error events. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Fault handling interrupt on reads disabled. 0b1 Fault handling interrupt on reads enabled. AU When ERR<n>FR.FI == '11' 3 3 3 Reserved, RES0. Otherwise UI 2 2 0 Uncorrected error recovery interrupt enable. When ERR<n>FR.UI == 0b10, this control applies to errors arising from both reads and writes. When enabled, the error recovery interrupt is generated for all errors recorded as Uncorrected error. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt disabled. 0b1 Error recovery interrupt enabled. AU When ERR<n>FR.UI == '10' RUI 2 2 0 Uncorrected error recovery interrupt on reads enable. When enabled, the error recovery interrupt is generated for errors recorded as Uncorrected error on reads. The interrupt is generated even if the error syndrome is discarded because the error record already records a higher priority error. 0b0 Error recovery interrupt on reads disabled. 0b1 Error recovery interrupt on reads enabled. AU When ERR<n>FR.UI == '11' 2 2 2 Reserved, RES0. Otherwise IMPLEMENTATION DEFINED 1 1 1 Reserved for IMPLEMENTATION DEFINED controls. Must permit SBZP write policy for software. ED 0 0 0 Error reporting and logging enable. When disabled, the node behaves as if error detection and correction are disabled, and no errors are recorded or signaled by the node. Arm recommends that, when disabled, correct error detection and correction codes are written for writes, unless disabled by an IMPLEMENTATION DEFINED control for error injection. It is IMPLEMENTATION DEFINED whether the node fully disables error detection and correction when reporting is disabled. That is, even with error reporting disabled, the node might continue to silently correct errors. Uncorrected errors might result in corrupt data being silently propagated by the node. If this node requires initialization after Cold reset to prevent signaling false errors, then Arm recommends this field is set to 0 on Cold reset, meaning errors are not reported from Cold reset. This allows boot software to initialize a node without signaling errors. Software can enable error reporting after the node is initialized. Otherwise, the Cold reset value is IMPLEMENTATION DEFINED. If the Cold reset value is 1, the reset values of other controls in this register are also IMPLEMENTATION DEFINED and should not be UNKNOWN. 0b0 Error reporting disabled. 0b1 Error reporting enabled. '0' '0' ID When ERR<n>FR.ED == '10' 0 0 0 Reserved, RES0. Otherwise 2026-03-26 20:27:25 2026-03_rel