ERR<n>MISC0 Error Record <n> Miscellaneous Register 0 when error record n is implemented 0 65534 RAS 0x020 + (64 * n) ERR<n>MISC0 RW IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain: Information to locate where the error was detected. If the error was detected within a FRU, the identity of the FRU. A Corrected error counter or counters. Other state information not present in the corresponding status and address registers. If the node that owns error record <n> implements a standard format Corrected error counter or counters (ERRFR[FirstRecordOfNode(n)].CEC != 0b000), then it is IMPLEMENTATION DEFINED whether error record <n> can record countable errors, and: If error record <n> records countable errors, then ERR<n>MISC0 implements the standard format Corrected error counter or counters for error record <n>. If error record <n> does not record countable errors, then it is recommended that the fields in ERR<n>MISC0 defined for the standard format counter or counters are RES0. That is, the fields behave like counters that never count. RAS ERRFR[FirstRecordOfNode(n)] describes the features implemented by the node that owns error record <n>. FirstRecordOfNode(n) is the index of the first error record owned by the same node as error record <n>. If the node owns a single record then FirstRecordOfNode(n) = n. For IMPLEMENTATION DEFINED fields in ERR<n>MISC0, writing zero returns the error record to an initial quiescent state. In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request. Fields that are read-only, nonzero, and ignore writes are compliant with this requirement. Arm recommends that any IMPLEMENTATION DEFINED syndrome field that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request is disabled at Cold reset and is enabled by software writing an IMPLEMENTATION DEFINED nonzero value to an IMPLEMENTATION DEFINED field in ERRCTLR[FirstRecordOfNode(n)]. ERR<n>MISC0 is a 64-bit register. When ERRFR[FirstRecordOfNode(n)].CEC == '000' or error record n does not record countable errors IMPLEMENTATION DEFINED 63 0 63:0 IMPLEMENTATION DEFINED syndrome. When ERRFR[FirstRecordOfNode(n)].CEC == '100', ERRFR[FirstRecordOfNode(n)].RP == '0', and error record n records countable errors IMPLEMENTATION DEFINED 63 48 63:48 IMPLEMENTATION DEFINED syndrome. OF 47 47 47 Sticky overflow bit. Set to 1 when ERR<n>MISC0.CEC is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Counter has not overflowed. 0b1 Counter has overflowed. AU CEC 46 32 46:32 Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted. AU IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED syndrome. When ERRFR[FirstRecordOfNode(n)].CEC == '010', ERRFR[FirstRecordOfNode(n)].RP == '0', and error record n records countable errors IMPLEMENTATION DEFINED 63 40 63:40 IMPLEMENTATION DEFINED syndrome. OF 39 39 39 Sticky overflow bit. Set to 1 when ERR<n>MISC0.CEC is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Counter has not overflowed. 0b1 Counter has overflowed. AU CEC 38 32 38:32 Corrected error count. Incremented for each Corrected error. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are counted. AU IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED syndrome. When ERRFR[FirstRecordOfNode(n)].CEC == '100', ERRFR[FirstRecordOfNode(n)].RP == '1', and error record n records countable errors OFO 63 63 63 Sticky overflow bit, other. Set to 1 when ERR<n>MISC0.CECO is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Other counter has not overflowed. 0b1 Other counter has overflowed. AU CECO 62 48 62:48 Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR. AU OFR 47 47 47 Sticky overflow bit, repeat. Set to 1 when ERR<n>MISC0.CECR is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Repeat counter has not overflowed. 0b1 Repeat counter has overflowed. AU CECR 46 32 46:32 Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors. For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way. AU IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED syndrome. When ERRFR[FirstRecordOfNode(n)].CEC == '010', ERRFR[FirstRecordOfNode(n)].RP == '1', and error record n records countable errors IMPLEMENTATION DEFINED 63 48 63:48 IMPLEMENTATION DEFINED syndrome. OFO 47 47 47 Sticky overflow bit, other. Set to 1 when ERR<n>MISC0.CECO is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Other counter has not overflowed. 0b1 Other counter has overflowed. AU CECO 46 40 46:40 Corrected error count, other. Incremented for each countable error that is not accounted for by incrementing ERR<n>MISC0.CECR. AU OFR 39 39 39 Sticky overflow bit, repeat. Set to 1 when ERR<n>MISC0.CECR is incremented and wraps through zero. A direct write that modifies this field might indirectly set ERR<n>STATUS.OF to an UNKNOWN value and a direct write to ERR<n>STATUS.OF that clears it to zero might indirectly set this field to an UNKNOWN value. 0b0 Repeat counter has not overflowed. 0b1 Repeat counter has overflowed. AU CECR 38 32 38:32 Corrected error count, repeat. Incremented for the first countable error, which also records other syndrome for the error, and subsequently for each countable error that matches the recorded other syndrome. Corrected errors are countable errors. It is IMPLEMENTATION DEFINED and might be UNPREDICTABLE whether Deferred and Uncorrected errors are countable errors. For example, the other syndrome might include the set and way information for an error detected in a cache. This might be recorded in the IMPLEMENTATION DEFINED ERR<n>MISC<m> fields on a first Corrected error. ERR<n>MISC0.CECR is then incremented for each subsequent Corrected Error in the same set and way. AU IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED syndrome. When ERRFR[FirstRecordOfNode(n)].CEC == '000' or error record n does not record countable errors When ERRFR[FirstRecordOfNode(n)].CEC == '100', ERRFR[FirstRecordOfNode(n)].RP == '0', and error record n records countable errors When ERRFR[FirstRecordOfNode(n)].CEC == '010', ERRFR[FirstRecordOfNode(n)].RP == '0', and error record n records countable errors When ERRFR[FirstRecordOfNode(n)].CEC == '100', ERRFR[FirstRecordOfNode(n)].RP == '1', and error record n records countable errors When ERRFR[FirstRecordOfNode(n)].CEC == '010', ERRFR[FirstRecordOfNode(n)].RP == '1', and error record n records countable errors Reads from ERR<n>MISC0 return an IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior. When the node that owns error record n implements the Common Fault Injection Mechanism, ERRPFGF[FirstRecordOfNode(n)].MV is 1, and ERR<n>STATUS.MV is 0, then syndrome fields in this register that are not updated by the node when an injected error is reported are RW. See ERR<n>PFGF.MV for more information. Otherwise, and for other fields in this register, Arm recommends that: Syndrome fields for multiple errors, such as a corrected error counter, are RW. Other syndrome fields specific to the most recently recorded error are accessible as follows: If ERR<n>STATUS.MV == 0, accesses to these fields are UNKNOWN/WI. If ERR<n>STATUS.MV == 1, accesses to these fields are RO. These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged. 2026-03-26 20:27:25 2026-03_rel