ERR<n>PFGCDN Error Record <n> Pseudo-fault Generation Countdown Register when error record n is implemented, the node that owns error record n implements the Common Fault Injection Model Extension, and error record n is the first error record in the node 0 65534 RAS 0x810 + (64 * n) ERR<n>PFGCDN RW Generates one of the errors enabled in the corresponding ERR<n>PFGCTL register. RAS ERR<n>FR describes the features implemented by the node. ERR<n>PFGCDN is a 64-bit register. 63 32 63:32 Reserved, RES0. CDN 31 0 31:0 Countdown value. This field is copied to Error Generation Counter when either: Software writes 1 to ERR<n>PFGCTL.CDNEN. The Error Generation Counter decrements to zero and ERR<n>PFGCTL.R is 1. While ERR<n>PFGCTL.CDNEN is 1 and the Error Generation Counter is nonzero, the counter decrements by 1 for each cycle at an IMPLEMENTATION DEFINED clock rate. When the counter reaches zero, one of the errors enabled in the ERR<n>PFGCTL register is generated. The current Error Generation Counter value is not visible to software. AU This section shows the offset of ERR<n>PFGCDN in an error record group when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, or ERR<n>PFGCDN is accessed in a fault injection group, see 'RAS memory-mapped register views' for the offset of ERR<n>PFGCDN. 2026-03-26 20:27:25 2026-03_rel