ERR<n>STATUS Error Record <n> Primary Status Register when error record n is implemented 0 65534 RAS 0x010 + (64 * n) ERR<n>STATUS When ERR<n>STATUS.V != '0', ERR<n>STATUS.V is not being cleared to 0b0 in the same write, and RAS System Architecture v1p1 is implemented RO When ERR<n>STATUS.UE != '0', ERR<n>STATUS.UE is not being cleared to 0b0 in the same write, and RAS System Architecture v1p1 is implemented RO When ERR<n>STATUS.OF != '0', ERR<n>STATUS.OF is not being cleared to 0b0 in the same write, and RAS System Architecture v1p1 is implemented RO When ERR<n>STATUS.CE != '00', ERR<n>STATUS.CE is not being cleared to 0b00 in the same write, and RAS System Architecture v1p1 is implemented RO When ERR<n>STATUS.DE != '0', ERR<n>STATUS.DE is not being cleared to 0b0 in the same write, and RAS System Architecture v1p1 is implemented RO RW When RAS System Architecture v2 is implemented, error record <n> might be one of the following: A continuation record containing more information about the error recorded in error record <n-1>. In this case, ERR<n>STATUS contains a subset of the values of a normal error record status register. A proxy for a different RAS agent. In this case, ERR<n>STATUS reports the status of the RAS agent. Otherwise, ERR<n>STATUS contains status information for error record <n>, including: Whether any error has been detected (valid). Whether any detected error was not corrected, and returned to a Requester. Whether any detected error was not corrected and deferred. Whether an error record has been discarded because additional errors have been detected before the first error was handled by software (overflow). Whether any error has been reported. Whether the other error record registers contain valid information. Whether the error was reported because poison data was detected or because a corrupt value was detected by an error detection code. A primary error code. An IMPLEMENTATION DEFINED extended error code. Within this register: ERR<n>STATUS.{AV, V, MV} are valid bits that define whether error record <n> registers are valid. ERR<n>STATUS.{UE, OF, CE, DE, UET} encode the types of error or errors recorded. ERR<n>STATUS.{CI, ER, PN, IERR, SERR} are syndrome fields. RAS ERRFRPFGF[FirstRecordOfNode(n)] describes the features implemented by the node that owns error record <n>. FirstRecordOfNode(n) is the index of the first error record owned by the same node as error record <n>. If the node owns a single record then FirstRecordOfNode(n) = n. For IMPLEMENTATION DEFINED fields in ERR<n>STATUS, writing zero returns the error record to an initial quiescent state. In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request. Fields that are read-only, nonzero, and ignore writes are compliant with this requirement. Arm recommends that any IMPLEMENTATION DEFINED syndrome field that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request is disabled at Cold reset and is enabled by software writing an IMPLEMENTATION DEFINED nonzero value to an IMPLEMENTATION DEFINED field in ERRCTLR[FirstRecordOfNode(n)]. ERR<n>STATUS is a 64-bit register. When RAS System Architecture v2 is implemented, ERR<n>FR.ED == '00', and ERR<n>FR.ERT == '01' Continuation record. 63 32 63:32 Reserved, RES0. AV 31 31 0 Address Valid. 0b0 ERR<n>ADDR not valid. 0b1 ERR<n>ADDR contains an additional address associated with the highest priority error recorded by this record. AU '0' W1C When error record n includes an address associated with an error 31 31 31 Reserved, RES0. Otherwise V 30 30 30 Status Register Valid. 0b0 ERR<n>STATUS not valid. 0b1 ERR<n>STATUS valid. Additional syndrome has been recorded. AU '0' W1C 29 29 29 Reserved, RAZ. 28 27 28:27 Reserved, RES0. MV 26 26 0 Miscellaneous Registers Valid. If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded. 0b0 ERR<n>MISC<m> not valid. 0b1 The contents of the ERR<n>MISC<m> registers contain additional information for an error recorded by this record. AU '0' W1C When error record <n> includes additional information for an error 26 26 26 Reserved, RES0. Otherwise 25 23 25:23 Reserved, RAZ. 22 20 22:20 Reserved, RES0. 19 19 19 Reserved, RAZ. 18 16 18:16 Reserved, RES0. IERR 15 8 15:8 IMPLEMENTATION DEFINED additional error code. Used with any primary error code ERR<n>STATUS.SERR value. Further IMPLEMENTATION DEFINED information can be placed in the ERR<n>MISC<m> registers. The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN. This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values. AU ERR<n>STATUS.V == '0' the node that owns error record n does not implement the Common Fault Injection Model Extension UNKNOWN/WI ERR<n>STATUS.V == '0' ERRPFGF[FirstRecordOfNode(n)].SYN == '0' UNKNOWN/WI RW 7 0 7:0 Reserved, RES0. When RAS System Architecture v2 is implemented, ERR<n>FR.ED == '11', and ERR<n>FR.ERT == '01' Proxy for a RAS agent. 63 31 63:31 Reserved, RES0. V 30 30 30 RAS agent error status. 0b0 RAS agent error status is not asserted. 0b1 RAS agent error status is asserted. RO ERI 29 29 29 RAS agent Error Recovery condition. 0b0 RAS agent error recovery condition is false. 0b1 RAS agent error recovery condition is true. RO 28 25 28:25 Reserved, RES0. FHI 24 24 24 RAS agent Fault Handling condition. 0b0 RAS agent fault handling condition is false. 0b1 RAS agent fault handling condition is true. RO 23 20 23:20 Reserved, RES0. CRI 19 19 19 RAS agent criticial error condition. 0b0 RAS agent criticial error condition is false. 0b1 RAS agent criticial error condition is true. RO 18 0 18:0 Reserved, RES0. When RAS System Architecture v1p1 is implemented Normal record, from FEAT_RASSAv1p1. 63 32 63:32 Reserved, RES0. AV 31 31 0 Address Valid. 0b0 ERR<n>ADDR not valid. 0b1 ERR<n>ADDR contains an address associated with the highest priority error recorded by this record. AU '0' W1C When error record n includes an address associated with an error 31 31 31 Reserved, RES0. Otherwise V 30 30 30 Status Register Valid. 0b0 ERR<n>STATUS not valid. 0b1 ERR<n>STATUS valid. At least one error has been recorded. AU '0' W1C UE 29 29 29 Uncorrected Error. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 No errors have been detected, or all detected errors have been either corrected or deferred. 0b1 At least one detected error was not corrected and not deferred. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C ER 28 28 0 Error Reported. An in-band error response signaled by the component might be masked and not generate any exception. It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as a Deferred error, but is not deferred to the Requester, can signal an in-band error response to the Requester, causing this field to be set to 1. 0b0 No in-band error response (External abort) signaled to the Requester making the access or other transaction. 0b1 An in-band error response was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true: The ERRCTLR[FirstRecordOfNode(n)].UE field, or applicable one of the ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE} fields, is implemented and was 1 when an error was detected and not corrected. The ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE, UE} fields are not implemented and the component always reports errors. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.[DE,UE] == '00' UNKNOWN/WI W1C When in-band error responses can be returned for a Deferred error ER 28 28 0 Error Reported. An in-band error response signaled by the component might be masked and not generate any exception. It is IMPLEMENTATION DEFINED whether an uncorrected error that is deferred and recorded as a Deferred error, but is not deferred to the Requester, can signal an in-band error response to the Requester, causing this field to be set to 1. 0b0 No in-band error response (External abort) signaled to the Requester making the access or other transaction. 0b1 An in-band error response was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true: The ERRCTLR[FirstRecordOfNode(n)].UE field, or applicable one of the ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE} fields, is implemented and was 1 when an error was detected and not corrected. The ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE, UE} fields are not implemented and the component always reports errors. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.UE == '0' UNKNOWN/WI W1C When in-band error responses are never returned for a Deferred error 28 28 28 Reserved, RES0. Otherwise OF 27 27 27 Overflow. Indicates that multiple errors have been detected. This field is set to 1 when one of the following occurs: A Corrected error counter is implemented, an error is counted, and the counter overflows. ERR<n>STATUS.V was previously 1, a Corrected error counter is not implemented, and a Corrected error is recorded. ERR<n>STATUS.V was previously 1, and a type of error other than a Corrected error is recorded. Otherwise, this field is unchanged when an error is recorded. If a Corrected error counter is implemented, then: A direct write that modifies the counter overflow flag indirectly might set this field to an UNKNOWN value. A direct write to this field that clears this field to zero might indirectly set the counter overflow flag to an UNKNOWN value. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 Since this field was last cleared to zero, no error syndrome has been discarded and, if a Corrected error counter is implemented, it has not overflowed. 0b1 Since this field was last cleared to zero, at least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C MV 26 26 0 Miscellaneous Registers Valid. If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded. 0b0 ERR<n>MISC<m> not valid. 0b1 The contents of the ERR<n>MISC<m> registers contain additional information for an error recorded by this record. AU '0' W1C When error record <n> includes additional information for an error 26 26 26 Reserved, RES0. Otherwise CE 25 24 25:24 Corrected Error. The mechanism by which a component or node detects whether a Corrected error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when a corrected error is recorded. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero. 0b00 No errors were corrected. 0b01 At least one transient error was corrected. 0b10 At least one error was corrected. 0b11 At least one persistent error was corrected. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C DE 23 23 23 Deferred Error. Support for deferring errors is IMPLEMENTATION DEFINED. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 No errors were deferred. 0b1 At least one error was not corrected and deferred. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C PN 22 22 22 Poison. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC), or Corrected error recorded. 0b1 Uncorrected error or Deferred error recorded because a poison value was detected. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.[DE,UE] == '00' UNKNOWN/WI W1C UET 21 20 21:20 Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error. UER can mean either Signaled or Recoverable error, and UEO can mean either Latent or Restartable error. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero. 0b00 Uncorrected error, Uncontainable error (UC). 0b01 Uncorrected error, Unrecoverable error (UEU). 0b10 Uncorrected error, Latent or Restartable error (UEO). 0b11 Uncorrected error, Signaled or Recoverable error (UER). AU ERR<n>STATUS.V == '0' ERR<n>STATUS.UE == '0' UNKNOWN/WI W1C CI 19 19 19 Critical Error. Indicates whether a critical error condition has been recorded. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 No critical error condition. 0b1 Critical error condition. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C RV 18 18 0 Reset Valid. When ERR<n>STATUS.V is 1, indicating the error record is valid, this field indicates whether the error was recorded before or after the most recent Error Recovery reset. This field is set to 0 when an error is recorded and either the fault overwrites the error syndrome, or the error record was previously not valid. 0b0 If the error record is valid then one or more errors have been recorded after the last Error Recovery reset. This error or errors might have overwritten lower priority errors recorded before the last Error Recovery reset. 0b1 If the error record is valid then one or more errors were recorded before the last Error Recovery reset. '1' W1C When RAS System Architecture v2 is implemented 18 18 18 Reserved, RES0. Otherwise RV2 17 17 0 Reset Valid 2. When ERR<n>STATUS.{V, RV} is {1, 1}, indicating the error record is valid and one or more errors were recorded before the last Error Recovery reset, this field indicates whether any lower severity errors have been recorded after the Error Recovery reset that did not overwrite the syndrome. This field is set to 0 when an error is recorded, including when the fault does not overwrite a previously recorded syndrome. 0b0 If the error record is valid then one or more errors were recorded after the last Error Recovery reset that did not overwrite the error syndrome. This includes errors that did not overwrite a previously recorded error syndrome. 0b1 If the error record is valid then one or more errors were recorded before the last Error Recovery reset. '1' W1C When RAS System Architecture v2 is implemented 17 17 17 Reserved, RES0. Otherwise 16 16 16 Reserved, RES0. IERR 15 8 15:8 IMPLEMENTATION DEFINED error code. Used with any primary error code ERR<n>STATUS.SERR value. Further IMPLEMENTATION DEFINED information can be placed in the ERR<n>MISC<m> registers. The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN. This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values. AU the node that owns error record n does not implement the Common Fault Injection Model Extension ERR<n>STATUS.V == '0' UNKNOWN/WI ERRPFGF[FirstRecordOfNode(n)].SYN == '0' ERR<n>STATUS.V == '0' UNKNOWN/WI RW SERR 7 0 7:0 Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry. All other values are reserved. The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN. This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values. 0x00 No error. 0x01 IMPLEMENTATION DEFINED error. 0x02 Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer. 0x03 IMPLEMENTATION DEFINED pin. For example, nSEI pin. 0x04 Assertion failure. For example, consistency failure. 0x05 Error detected on internal data path. For example, parity on ALU result. 0x06 Data value from associative memory. For example, ECC error on cache data. 0x07 Address/control value from associative memory. For example, ECC error on cache tag. 0x08 Data value from a TLB. For example, ECC error on TLB data. 0x09 Address/control value from a TLB. For example, ECC error on TLB tag. 0x0A Data value from producer. For example, parity error on write data bus. 0x0B Address/control value from producer. For example, parity error on address bus. 0x0C Data value from (non-associative) external memory. For example, ECC error in SDRAM. 0x0D Illegal address (software fault). For example, access to unpopulated memory. 0x0E Illegal access (software fault). For example, byte write to word register. 0x0F Illegal state (software fault). For example, device not ready. 0x10 Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, SVE, and SME registers are data registers. 0x11 Internal control register. For example, parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, SVE, and SME registers are control registers. 0x12 Error response from Completer of access. For example, error response from cache write-back. 0x13 External timeout. For example, timeout on interaction with another component. 0x14 Internal timeout. For example, timeout on interface within the component. 0x15 Deferred error from Completer not supported at Requester. For example, poisoned data received from the Completer of an access by a Requester that cannot defer the error further. 0x16 Deferred error from Requester not supported at Completer. For example, poisoned data received from the Requester of an access by a Completer that cannot defer the error further. 0x17 Deferred error from Completer passed through. For example, poisoned data received from the Completer of an access and returned to the Requester. 0x18 Deferred error from Requester passed through. For example, poisoned data received from the Requester of an access and deferred to the Completer. 0x19 Error recorded by PCIe error logs. Indicates that the component has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe. 0x1A Other internal error. For example, parity error on internal state of the component that is not covered by another primary error code. AU the node that owns error record n does not implement the Common Fault Injection Model Extension ERR<n>STATUS.V == '0' UNKNOWN/WI ERRPFGF[FirstRecordOfNode(n)].SYN == '0' ERR<n>STATUS.V == '0' UNKNOWN/WI RW Normal record, when FEAT_RASSAv1p1 is not implemented. 63 32 63:32 Reserved, RES0. AV 31 31 0 Address Valid. 0b0 ERR<n>ADDR not valid. 0b1 ERR<n>ADDR contains an address associated with the highest priority error recorded by this record. '0' ERR<n>STATUS.[DE,UE] == '00' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C When error record n includes an address associated with an error 31 31 31 Reserved, RES0. Otherwise V 30 30 30 Status Register Valid. 0b0 ERR<n>STATUS not valid. 0b1 ERR<n>STATUS valid. At least one error has been recorded. '0' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C UE 29 29 29 Uncorrected Error. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 No errors have been detected, or all detected errors have been either corrected or deferred. 0b1 At least one detected error was not corrected and not deferred. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI ERR<n>STATUS.OF == '1' ERR<n>STATUS.OF is not being cleared to 0b0 in the same write RO W1C ER 28 28 0 Error Reported. If this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero, when any of: Clearing ERR<n>STATUS.V to 0. Clearing both ERR<n>STATUS.{DE, UE} to 0. 0b0 No in-band error response (External abort) signaled to the Requester making the access or other transaction. 0b1 An in-band error response was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true: The ERRCTLR[FirstRecordOfNode(n)].UE field, or applicable one of the ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE} fields, is implemented and was 1 when an error was detected and not corrected. The ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE, UE} fields are not implemented and the component always reports errors. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.[DE,UE] == '00' UNKNOWN/WI ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO W1C When in-band error responses can be returned for a Deferred error ER 28 28 0 Error Reported. If this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero, when any of: Clearing ERR<n>STATUS.V to 0. Clearing ERR<n>STATUS.UE to 0. 0b0 No in-band error response (External abort) signaled to the Requester making the access or other transaction. 0b1 An in-band error response was signaled by the component to the Requester making the access or other transaction. This can be because any of the following are true: The ERRCTLR[FirstRecordOfNode(n)].UE field, or applicable one of the ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE} fields, is implemented and was 1 when an error was detected and not corrected. The ERRCTLR[FirstRecordOfNode(n)].{WUE, RUE, UE} fields are not implemented and the component always reports errors. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.UE == '0' UNKNOWN/WI ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C When in-band error responses are never returned for a Deferred error 28 28 28 Reserved, RES0. Otherwise OF 27 27 27 Overflow. Indicates that multiple errors have been detected. This field is set to 1 when one of the following occurs: An Uncorrected error is detected and ERR<n>STATUS.UE == 1. A Deferred error is detected, ERR<n>STATUS.UE == 0 and ERR<n>STATUS.DE == 1. A Corrected error is detected, no Corrected error counter is implemented, ERR<n>STATUS.UE == 0, ERR<n>STATUS.DE == 0, and ERR<n>STATUS.CE != 0b00. ERR<n>STATUS.CE might be updated for the new Corrected error. A Corrected error counter is implemented, ERR<n>STATUS.UE == 0, ERR<n>STATUS.DE == 0, and the counter overflows. It is IMPLEMENTATION DEFINED whether this field is set to 1 when one of the following occurs: A Deferred error is detected and ERR<n>STATUS.UE == 1. A Corrected error is detected, no Corrected error counter is implemented, and ERR<n>STATUS.{UE, DE} != {0, 0}. A Corrected error counter is implemented, ERR<n>STATUS.{UE, DE} != {0, 0}, and the counter overflows. It is IMPLEMENTATION DEFINED whether this field is cleared to 0 when one of the following occurs: An Uncorrected error is detected and ERR<n>STATUS.UE == 0. A Deferred error is detected, ERR<n>STATUS.UE == 0, and ERR<n>STATUS.DE == 0. A Corrected error is detected, ERR<n>STATUS.UE == 0, ERR<n>STATUS.DE == 0, and ERR<n>STATUS.CE == 0b00. The IMPLEMENTATION DEFINED clearing of this field might also depend on the value of the other error status fields. If a Corrected error counter is implemented, then: A direct write that modifies the counter overflow flag indirectly might set this field to an UNKNOWN value. A direct write to this field that clears this field to 0 might indirectly set the counter overflow flag to an UNKNOWN value. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 If ERR<n>STATUS.UE == 1, then no error syndrome for an Uncorrected error has been discarded. If ERR<n>STATUS.UE == 0 and ERR<n>STATUS.DE == 1, then no error syndrome for a Deferred error has been discarded. If ERR<n>STATUS.UE == 0, ERR<n>STATUS.DE == 0, and a Corrected error counter is implemented, then the counter has not overflowed. If ERR<n>STATUS.UE == 0, ERR<n>STATUS.DE == 0, ERR<n>STATUS.CE != 0b00, and no Corrected error counter is implemented, then no error syndrome for a Corrected error has been discarded. This field might have been set to 1 when an error syndrome was discarded and later cleared to 0 when a higher priority syndrome was recorded. 0b1 At least one error syndrome has been discarded or, if a Corrected error counter is implemented, it might have overflowed. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI W1C MV 26 26 0 Miscellaneous Registers Valid. If the ERR<n>MISC<m> registers can contain additional information for a previously recorded error, then the contents must be self-describing to software or a user. For example, certain fields might relate only to Corrected errors, and other fields only to the most recent error that was not discarded. 0b0 ERR<n>MISC<m> not valid. 0b1 The contents of the ERR<n>MISC<m> registers contain additional information for an error recorded by this record. '0' ERR<n>STATUS.[DE,UE] == '00' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C When error record <n> includes additional information for an error 26 26 26 Reserved, RES0. Otherwise CE 25 24 25:24 Corrected Error. The mechanism by which a component or node detects whether a Corrected error is transient or persistent is IMPLEMENTATION DEFINED. If no such mechanism is implemented, then the node sets this field to 0b10 when a corrected error is recorded. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero. 0b00 No errors were corrected. 0b01 At least one transient error was corrected. 0b10 At least one error was corrected. 0b11 At least one persistent error was corrected. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI ERR<n>STATUS.OF == '1' ERR<n>STATUS.OF is not being cleared to 0b0 in the same write RO W1C DE 23 23 23 Deferred Error. Support for deferring errors is IMPLEMENTATION DEFINED. When clearing ERR<n>STATUS.V to 0, if this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero. 0b0 No errors were deferred. 0b1 At least one error was not corrected and deferred. AU When ERR<n>STATUS.V == '0' UNKNOWN/WI ERR<n>STATUS.OF == '1' ERR<n>STATUS.OF is not being cleared to 0b0 in the same write RO W1C PN 22 22 22 Poison. If this field is nonzero, then Arm recommends that software write 1 to this field to clear this field to zero, when any of: Clearing ERR<n>STATUS.V to 0. Clearing both ERR<n>STATUS.{DE, UE} to 0. 0b0 Uncorrected error or Deferred error recorded because a corrupt value was detected, for example, by an error detection code (EDC), or Corrected error recorded. 0b1 Uncorrected error or Deferred error recorded because a poison value was detected. AU ERR<n>STATUS.V == '0' ERR<n>STATUS.[DE,UE] == '00' UNKNOWN/WI ERR<n>STATUS.[DE,UE] == '00' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C UET 21 20 21:20 Uncorrected Error Type. Describes the state of the component after detecting or consuming an Uncorrected error. UER can mean either Signaled or Recoverable error, and UEO can mean either Latent or Restartable error. If this field is nonzero, then Arm recommends that software write ones to this field to clear this field to zero, when any of: Clearing ERR<n>STATUS.V to 0. Clearing ERR<n>STATUS.UE to 0. 0b00 Uncorrected error, Uncontainable error (UC). 0b01 Uncorrected error, Unrecoverable error (UEU). 0b10 Uncorrected error, Latent or Restartable error (UEO). 0b11 Uncorrected error, Signaled or Recoverable error (UER). AU ERR<n>STATUS.V == '0' ERR<n>STATUS.UE == '0' UNKNOWN/WI ERR<n>STATUS.[DE,UE] == '00' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO W1C 19 16 19:16 Reserved, RES0. IERR 15 8 15:8 IMPLEMENTATION DEFINED error code. Used with any primary error code ERR<n>STATUS.SERR value. Further IMPLEMENTATION DEFINED information can be placed in the ERR<n>MISC<m> registers. The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN. This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values. AU the node that owns error record n does not implement the Common Fault Injection Model Extension ERR<n>STATUS.V == '0' UNKNOWN/WI ERRPFGF[FirstRecordOfNode(n)].SYN == '0' ERR<n>STATUS.V == '0' UNKNOWN/WI ERR<n>STATUS.[DE,UE] == '00' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO RW SERR 7 0 7:0 Architecturally-defined primary error code. The primary error code might be used by a fault handling agent to triage an error without requiring device-specific code. For example, to count and threshold corrected errors in software, or generate a short log entry. All other values are reserved. The implemented set of valid values that this field can take is IMPLEMENTATION DEFINED. If any value not in this set is written to this register, then the value read back from this field is UNKNOWN. This means that one or more bits of this field might be implemented as fixed read-as-zero or read-as-one values. 0x00 No error. 0x01 IMPLEMENTATION DEFINED error. 0x02 Data value from (non-associative) internal memory. For example, ECC from on-chip SRAM or buffer. 0x03 IMPLEMENTATION DEFINED pin. For example, nSEI pin. 0x04 Assertion failure. For example, consistency failure. 0x05 Error detected on internal data path. For example, parity on ALU result. 0x06 Data value from associative memory. For example, ECC error on cache data. 0x07 Address/control value from associative memory. For example, ECC error on cache tag. 0x08 Data value from a TLB. For example, ECC error on TLB data. 0x09 Address/control value from a TLB. For example, ECC error on TLB tag. 0x0A Data value from producer. For example, parity error on write data bus. 0x0B Address/control value from producer. For example, parity error on address bus. 0x0C Data value from (non-associative) external memory. For example, ECC error in SDRAM. 0x0D Illegal address (software fault). For example, access to unpopulated memory. 0x0E Illegal access (software fault). For example, byte write to word register. 0x0F Illegal state (software fault). For example, device not ready. 0x10 Internal data register. For example, parity on a SIMD&FP register. For a PE, all general-purpose, stack pointer, SIMD&FP, SVE, and SME registers are data registers. 0x11 Internal control register. For example, parity on a System register. For a PE, all registers other than general-purpose, stack pointer, SIMD&FP, SVE, and SME registers are control registers. 0x12 Error response from Completer of access. For example, error response from cache write-back. 0x13 External timeout. For example, timeout on interaction with another component. 0x14 Internal timeout. For example, timeout on interface within the component. 0x15 Deferred error from Completer not supported at Requester. For example, poisoned data received from the Completer of an access by a Requester that cannot defer the error further. 0x16 Deferred error from Requester not supported at Completer. For example, poisoned data received from the Requester of an access by a Completer that cannot defer the error further. 0x17 Deferred error from Completer passed through. For example, poisoned data received from the Completer of an access and returned to the Requester. 0x18 Deferred error from Requester passed through. For example, poisoned data received from the Requester of an access and deferred to the Completer. 0x19 Error recorded by PCIe error logs. Indicates that the component has recorded an error in a PCIe error log. This might be the PCIe device status register, AER, DVSEC, or other mechanisms defined by PCIe. 0x1A Other internal error. For example, parity error on internal state of the component that is not covered by another primary error code. AU the node that owns error record n does not implement the Common Fault Injection Model Extension ERR<n>STATUS.V == '0' UNKNOWN/WI ERRPFGF[FirstRecordOfNode(n)].SYN == '0' ERR<n>STATUS.V == '0' UNKNOWN/WI ERR<n>STATUS.DE == '0' ERR<n>STATUS.UE == '0' ERR<n>STATUS.CE != '00' ERR<n>STATUS.CE is not being cleared to 0b00 in the same write RO ERR<n>STATUS.UE == '0' ERR<n>STATUS.DE != '0' ERR<n>STATUS.DE is not being cleared to 0b0 in the same write RO ERR<n>STATUS.UE != '0' ERR<n>STATUS.UE is not being cleared to 0b0 in the same write RO RW When RAS System Architecture v2 is implemented, ERR<n>FR.ED == '00', and ERR<n>FR.ERT == '01' When RAS System Architecture v2 is implemented, ERR<n>FR.ED == '11', and ERR<n>FR.ERT == '01' When RAS System Architecture v1p1 is implemented ERR<n>STATUS.{AV, V, UE, ER, OF, MV, CE, DE, PN, UET, CI} are write-one-to-clear (W1C) fields, meaning writes of zero are ignored, and a write of one or all-ones to the field clears the field to zero. ERR<n>STATUS.{IERR, SERR} are read/write (RW) fields, although the set of implemented valid values is IMPLEMENTATION DEFINED. See also ERR<n>PFGF.SYN. After reading ERR<n>STATUS, software must clear the valid fields in the register to allow new errors to be recorded. However, between reading the register and clearing the valid fields, a new error might have overwritten the register. To prevent this error being lost by software, the register prevents updates to fields that might have been updated by a new error. When RAS System Architecture v1.0 is implemented: Writes to ERR<n>STATUS.{UE, DE, CE} are ignored if ERR<n>STATUS.OF is 1 and is not being cleared to 0. Writes to ERR<n>STATUS.V are ignored if any of ERR<n>STATUS.{UE, DE, CE} are nonzero and are not being cleared to zero. Writes to ERR<n>STATUS.{AV, MV} and the ERR<n>STATUS.{ER, PN, UET, IERR, SERR} syndrome fields are ignored if the highest priority nonzero error status field is not being cleared to zero. The error status fields in priority order from highest to lowest, are ERR<n>STATUS.UE, ERR<n>STATUS.DE, and ERR<n>STATUS.CE. When RAS System Architecture v1.1 is implemented, a write to the register is ignored if all of: Any of ERR<n>STATUS.{V, UE, OF, CE, DE} are nonzero before the write. The write does not clear the nonzero ERR<n>STATUS.{V, UE, OF, CE, DE} fields to zero by writing ones to the applicable field or fields. Some of the fields in ERR<n>STATUS are also defined as UNKNOWN where certain combinations of ERR<n>STATUS.{V, DE, UE} are zero. The rules for writes to ERR<n>STATUS allow a node to implement such a field as a fixed read-only value. For example, when RAS System Architecture v1.1 is implemented, a write to ERR<n>STATUS when ERR<n>STATUS.V is 1 results in either ERR<n>STATUS.V field being cleared to zero, or ERR<n>STATUS.V not changing. Since all fields in ERR<n>STATUS, other than ERR<n>STATUS.{AV, V, MV}, usually read as UNKNOWN values when ERR<n>STATUS.V is zero, this means those fields can be implemented as read-only if applicable. To ensure correct and portable operation, when software is clearing the valid fields in the register to allow new errors to be recorded, Arm recommends that software performs the following sequence of operations in order: Read ERR<n>STATUS and determine which fields need to be cleared to zero. In a single write to ERR<n>STATUS: Write ones to all the W1C fields that are nonzero in the read value. Write zero to all the W1C fields that are zero in the read value. Write zero to all the RW fields. Read back ERR<n>STATUS after the write to confirm no new fault has been recorded. Otherwise, these fields might not have the correct value when a new fault is recorded. 2026-03-26 20:27:25 2026-03_rel