GICC_AHPPIR CPU Interface Aliased Highest Priority Pending Interrupt Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x0028 GICC_AHPPIR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO If the highest priority pending interrupt is in Group 1, this register provides the INTID of the highest priority pending interrupt on the CPU interface. GICC If GICD_CTLR.DS==0, this register is an alias of the Non-secure view of GICC_HPPIR. A Secure access to this register is identical to a Non-secure access to GICC_HPPIR. GICC_AHPPIR is a 32-bit register. 31 24 31:24 Reserved, RES0. INTID 23 0 23:0 The INTID of the signaled interrupt. INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled: Bits [23:13] are RES0. For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_HPPIR1 provides equivalent functionality. For AArch64 implementations, ICC_HPPIR1_EL1 provides equivalent functionality. If the highest priority pending interrupt is in Group 0, a read of this register returns the special INTID 1023. Interrupt identifiers corresponding to an interrupt group that is not enabled are ignored. If the highest priority pending interrupt is a direct interrupt that is both individually enabled in the Distributor and part of an interrupt group that is enabled in the Distributor, and the interrupt group is disabled in the CPU interface for this PE, this register returns the special INTID 1023. For more information about pending interrupts that are not considered when determining the highest priority pending interrupt, see 'Preemption' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC. 2026-03-26 20:27:25 2026-03_rel