GICC_AIAR CPU Interface Aliased Interrupt Acknowledge Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x0020 GICC_AIAR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO Provides the INTID of the signaled Group 1 interrupt. A read of this register by the PE acts as an acknowledge for the interrupt. GICC When GICD_CTLR.DS==0, this register is an alias of the Non-secure view of GICC_IAR. A Secure access to this register is identical to a Non-secure access to GICC_IAR. GICC_AIAR is a 32-bit register. 31 24 31:24 Reserved, RES0. INTID 23 0 23:0 The INTID of the signaled interrupt. INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled: Bits [23:13] are RES0. For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0. When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC. 2026-03-26 20:27:25 2026-03_rel