<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>GICC_BPR</reg_short_name>
        
        <reg_long_name>CPU Interface Binary Point Register</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_GICv3_LEGACY is implemented</reg_condition>
      

    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>GIC CPU interface</reg_component>
    <reg_offset><hexnumber>0x0008</hexnumber></reg_offset>
    <reg_instance>GICC_BPR</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When GICD_CTLR.DS == '0'</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_level>When an access is Secure</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_level>When an access is Non-secure</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>GICC</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>In systems that support two Security states:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>This register is Banked.</content>
</listitem><listitem><content>The Secure instance of this register determines Group 0 interrupt preemption.</content>
</listitem><listitem><content>The Non-secure instance of this register determines Group 1 interrupt preemption.</content>
</listitem></list>

      </configuration_text>
      <configuration_text>
        <para>In systems that support only one Security state, when <register_link state="ext" id="ext-gicc_ctlr.xml">GICC_CTLR</register_link>.CBPR == 0, this register determines only Group 0 interrupt preemption.</para>

      </configuration_text>
      <configuration_text>
        <para>When <register_link state="ext" id="ext-gicc_ctlr.xml">GICC_CTLR</register_link>.CBPR == 1, this register determines interrupt preemption for both Group 0 and Group 1 interrupts.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>GICC_BPR is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_3" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>3</field_lsb>
    <rel_range>31:3</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-2_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>Binary_Point</field_name>
    <field_msb>2</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>2:0</rel_range>
    <field_description order="before"><para>Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:</para>
<list type="unordered">
<listitem><content><xref filename="AS_interrupt_handling_and_prioritization.fm" linkend="CJHEAFIJ">'Secure ICC_BPR1_EL1 Binary Point when CBPR == 0' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</xref>, for the processing of Group 1 interrupts in a GIC implementation that supports interrupt grouping, when <register_link state="ext" id="ext-gicc_ctlr.xml">GICC_CTLR</register_link>.CBPR == 0.</content>
</listitem><listitem><content><xref filename="AS_interrupt_handling_and_prioritization.fm" linkend="CJHIIGAD">'Non-secure ICC_BPR1_EL1 Binary Point when CBPR == 0' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</xref>, for all other cases.</content>
</listitem></list></field_description>
    <field_resets>
      <field_reset reset_type="Warm">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields>
    <note>
      <para>Aliasing the Non-secure GICC_BPR as <register_link state="ext" id="ext-gicc_abpr.xml">GICC_ABPR</register_link> in a multiprocessor system permits a PE that can make only Secure accesses to configure the preemption setting for Group 1 interrupts by accessing <register_link state="ext" id="ext-gicc_abpr.xml">GICC_ABPR</register_link>.</para>
    </note>
  </text_after_fields>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_3" msb="31" lsb="3"/>
  <fieldat id="fieldset_0-2_0" msb="2" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>This register is used only when System register access is not enabled. When System register access is enabled this register is RAZ/WI, and the System registers <register_link state="AArch64" id="AArch64-icc_bpr0_el1.xml">ICC_BPR0_EL1</register_link> and <register_link state="AArch64" id="AArch64-icc_bpr1_el1.xml">ICC_BPR1_EL1</register_link> provide equivalent functionality.</para>
      </access_permission_text>





    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>