GICC_CTLR CPU Interface Control Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x0000 GICC_CTLR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Controls the CPU interface, including enabling of interrupt groups, interrupt signal bypass, binary point registers used, and separation of priority drop and interrupt deactivation. If the GIC implementation supports two Security states, independent EOI controls are provided for accesses from each Security state. Secure accesses handle both Group 0 and Group 1 interrupts, and Non-secure accesses handle Group 1 interrupts only. GICC In a GIC implementation that supports two Security states: This register is Banked. The register bit assignments are different in the Secure and Non-secure copies. GICC_CTLR is a 32-bit register. When GICD_CTLR.DS==0, Non-secure access GICD_CTLR.DS==0, Non-secure access 31 10 31:10 Reserved, RES0. EOImodeNS 9 9 9 Controls the behavior of Non-secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR. An implementation is permitted to make this bit RAO/WI. 0b0 GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. 0b1 GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. '0' 8 7 8:7 Reserved, RES0. IRQBypDisGrp1 6 6 6 When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass IRQ signal is signaled to the PE. 0b1 The bypass IRQ signal is not signaled to the PE. '0' FIQBypDisGrp1 5 5 5 When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass FIQ signal is signaled to the PE. 0b1 The bypass FIQ signal is not signaled to the PE. '0' 4 1 4:1 Reserved, RES0. EnableGrp1 0 0 0 This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE: 0b0 Group 1 interrupt signaling is disabled. 0b1 Group 1 interrupt signaling is enabled. '0' When GICD_CTLR.DS==0, Secure access GICD_CTLR.DS==0, Secure access 31 11 31:11 Reserved, RES0. EOImodeNS 10 10 10 Controls the behavior of Non-secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR. An implementation is permitted to make this bit RAO/WI. 0b0 GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. 0b1 GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. '0' EOImodeS 9 9 9 Controls the behavior of Secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR. An implementation is permitted to make this bit RAO/WI. This field shares state with GICC_CTLR.EOImode. 0b0 GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. 0b1 GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. '0' IRQBypDisGrp1 8 8 8 When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass IRQ signal is signaled to the PE. 0b1 The bypass IRQ signal is not signaled to the PE. '0' FIQBypDisGrp1 7 7 7 When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass FIQ signal is signaled to the PE. 0b1 The bypass FIQ signal is not signaled to the PE. '0' IRQBypDisGrp0 6 6 6 When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 0: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass IRQ signal is signaled to the PE. 0b1 The bypass IRQ signal is not signaled to the PE. '0' FIQBypDisGrp0 5 5 5 When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 0: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass FIQ signal is signaled to the PE. 0b1 The bypass FIQ signal is not signaled to the PE. '0' CBPR 4 4 4 Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts: This field is an alias of ICC_CTLR_EL3.CBPR_EL1NS. In a GIC that supports two Security states, when CBPR == 1: A Non-secure read of GICC_BPR returns the value of Secure GICC_BPR.Binary_Point, incremented by 1, and saturated to 0b111. Non-secure writes of GICC_BPR are ignored. 0b0 GICC_BPR determines preemption for Group 0 interrupts only. GICC_ABPR determines preemption for Group 1 interrupts. 0b1 GICC_BPR determines preemption for both Group 0 and Group 1 interrupts. '0' FIQEn 3 3 3 Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal: Group 1 interrupts are signaled using the IRQ signal only. If an implementation supports two Security states, this bit is permitted to be RAO/WI. 0b0 Group 0 interrupts are signaled using the IRQ signal. 0b1 Group 0 interrupts are signaled using the FIQ signal. '0' 2 2 2 Reserved, RES0. EnableGrp1 1 1 1 This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE: 0b0 Group 1 interrupt signaling is disabled. 0b1 Group 1 interrupt signaling is enabled. '0' EnableGrp0 0 0 0 Enables the signaling of Group 0 interrupts by the CPU interface to a target PE: 0b0 Group 0 interrupt signaling is disabled. 0b1 Group 0 interrupt signaling is enabled. '0' When GICD_CTLR.DS == '1' GICD_CTLR.DS==1 31 10 31:10 Reserved, RES0. EOImode 9 9 9 Controls the behavior of accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR. An implementation is permitted to make this bit RAO/WI. This field shares state with GICC_CTLR.EOImodeS. 0b0 GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. 0b1 GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. '0' IRQBypDisGrp1 8 8 8 When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass IRQ signal is signaled to the PE. 0b1 The bypass IRQ signal is not signaled to the PE. '0' FIQBypDisGrp1 7 7 7 When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1: If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass FIQ signal is signaled to the PE. 0b1 The bypass FIQ signal is not signaled to the PE. '0' IRQBypDisGrp0 6 6 6 When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 0: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass IRQ signal is signaled to the PE. 0b1 The bypass IRQ signal is not signaled to the PE. '0' FIQBypDisGrp0 5 5 5 When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 0: If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI. If System register access is enabled for EL1, this field is ignored. If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI. For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 The bypass FIQ signal is signaled to the PE. 0b1 The bypass FIQ signal is not signaled to the PE. '0' CBPR 4 4 4 Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts: This field is an alias of ICC_CTLR_EL3.CBPR_EL1NS. In a GIC that supports two Security states, when CBPR == 1: A Non-secure read of GICC_BPR returns the value of Secure GICC_BPR.Binary_Point, incremented by 1, and saturated to 0b111. Non-secure writes of GICC_BPR are ignored. 0b0 GICC_BPR determines preemption for Group 0 interrupts only. GICC_ABPR determines preemption for Group 1 interrupts. 0b1 GICC_BPR determines preemption for both Group 0 and Group 1 interrupts. '0' FIQEn 3 3 3 Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal: Group 1 interrupts are signaled using the IRQ signal only. If an implementation supports two Security states, this bit is permitted to be RAO/WI. 0b0 Group 0 interrupts are signaled using the IRQ signal. 0b1 Group 0 interrupts are signaled using the FIQ signal. '0' 2 2 2 Reserved, RES0. EnableGrp1 1 1 1 This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE: 0b0 Group 1 interrupt signaling is disabled. 0b1 Group 1 interrupt signaling is enabled. '0' EnableGrp0 0 0 0 Enables the signaling of Group 0 interrupts by the CPU interface to a target PE: 0b0 Group 0 interrupt signaling is disabled. 0b1 Group 0 interrupt signaling is enabled. '0' When GICD_CTLR.DS==0, Non-secure access When GICD_CTLR.DS==0, Secure access When GICD_CTLR.DS == '1' This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_CTLR and ICC_MCTLR provide equivalent functionality. For AArch64 implementations, ICC_CTLR_EL1 and ICC_CTLR_EL3 provide equivalent functionality. 2026-03-26 20:27:25 2026-03_rel