GICC_DIR CPU Interface Deactivate Interrupt Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x1000 GICC_DIR When GICD_CTLR.DS == '0' WO When an access is Secure WO When an access is Non-secure WO When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt. GICC GICC_DIR is a 32-bit register. 31 24 31:24 Reserved, RES0. INTID 23 0 23:0 The INTID of the signaled interrupt. INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled: Bits [23:13] are RES0. For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_DIR provides equivalent functionality. For AArch64 implementations, ICC_DIR_EL1 provides equivalent functionality. Writes to this register have an effect only in the following cases: When GICD_CTLR.DS == 1, if GICC_CTLR.EOImode == 1. In GIC implementations that support two Security states: If the access is Secure and GICC_CTLR.EOImodeS == 1. If the access is Non-secure and GICC_CTLR.EOImodeNS == 1. The following writes must be ignored: Writes to this register when the corresponding EOImode field in GICC_CTLR == 0. In systems that support system error generation, an implementation might generate a system error. Writes to this register when the corresponding EOImode field in GICC_CTLR == 0 and the corresponding interrupt is not active. In systems that support system error generation, an implementation might generate a system error. In implementations using the GIC Stream Protocol Interface, these writes correspond to a Deactivate packet for an interrupt that is not active. For more information, see 'Deactivate (ICC)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). If the corresponding EOImode field in GICC_CTLR is 1 and this register is written to without a corresponding write to GICC_EOIR or GICC_AEOIR, the interrupt is deactivated but the bit corresponding to it in the active priorities registers remains set. When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC. 2026-03-26 20:27:25 2026-03_rel