GICC_IIDR CPU Interface Identification Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x00FC GICC_IIDR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO Provides information about the implementer and revision of the CPU interface. GICC GICC_IIDR is a 32-bit register. ProductID 31 20 31:20 Product Identifier. This field has an IMPLEMENTATION DEFINED value. RO Architecture_version 19 16 19:16 The version of the GIC architecture that is implemented. Other values are reserved. 0b0001 GICv1. 0b0010 GICv2. 0b0011 FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. 0b0100 FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. RO Revision 15 12 15:12 Revision number for the CPU interface. This field has an IMPLEMENTATION DEFINED value. RO Implementer 11 0 11:0 Contains the JEP106 manufacturer's identification code of the designer of the CPU interface. The code identifies the designer of the component, which might not be the same as the implementer of the device containing the component. Zero is not a valid JEP106 identification code, meaning a value of zero for GICC_IIDR indicates this register is not implemented. For an implementation designed by Arm, this field reads as 0x43B. Bits [11:8] contain the JEP106 bank identifier of the designer minus 1. Bit 7 is RES0. Bits [6:0] contain bits [6:0] of the JEP106 manufacturer's identification code of the designer. This field has an IMPLEMENTATION DEFINED value. RO 2026-03-26 20:27:25 2026-03_rel