GICC_NSAPR<n> CPU Interface Non-secure Active Priorities Registers when FEAT_GICv3_LEGACY is implemented 0 3 GIC CPU interface 0x00E0 + (4 * n) GICC_NSAPR<n> When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Provides information about Group 1 interrupt active priorities. GICC The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active. When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses. GICC_NSAPR1 is implemented only in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are implemented only in implementations that support 7 bits of priority. GICC_NSAPR<n> is a 32-bit register. IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. 0x00000000 2026-03-26 20:27:25 2026-03_rel