GICC_PMR CPU Interface Priority Mask Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x0004 GICC_PMR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW This register provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE. Higher interrupt priority corresponds to a lower value of the Priority field. GICC This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common. GICC_PMR is a 32-bit register. 31 8 31:8 Reserved, RES0. Priority 7 0 7:0 The priority mask level for the CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE. If the GIC implementation supports fewer than 256 priority levels, some bits might be RAZ/WI as follows: For 128 supported levels, bit [0] = 0b0. For 64 supported levels, bits [1:0] = 0b00. For 32 supported levels, bits [2:0] = 0b000. For 16 supported levels, bits [3:0] = 0b0000. For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). AU If the GIC implementation supports two Security states: Non-secure accesses to this register can only read or write values corresponding to the lower half of the priority range. If a Secure write has programmed the register with a value that corresponds to a value in the upper half of the priority range, then: Any Non-secure read of the register returns 0x00, regardless of the value held in the register. Non-secure writes are ignored. For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 2026-03-26 20:27:25 2026-03_rel