GICC_STATUSR CPU Interface Status Register when FEAT_GICv3_LEGACY is implemented GIC CPU interface 0x002C GICC_STATUSR (S) When GICD_CTLR.DS == '0' RW When an access is Secure RW GIC CPU interface 0x002C GICC_STATUSR (NS) When GICD_CTLR.DS == '0' RW When an access is Non-secure RW Provides software with a mechanism to detect: Accesses to reserved locations. Writes to read-only locations. Reads of write-only locations. GICC If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies. This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions. GICC_STATUSR is a 32-bit register. 31 5 31:5 Reserved, RES0. ASV 4 4 4 Attempted security violation. This bit is not set to 1 for registers where any of the fields are Non-secure. 0b0 Normal operation. 0b1 A Non-secure access to a Secure register has been detected. WROD 3 3 3 Write to an RO location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A write to an RO location has been detected. RWOD 2 2 2 Read of a WO location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A read of a WO location has been detected. WRD 1 1 1 Write to a reserved location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A write to a reserved location has been detected. RRD 0 0 0 Read of a reserved location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A read of a reserved location has been detected. This is an optional register. If the register is not implemented, the location is RAZ/WI. If this register is implemented, GICV_STATUSR must also be implemented. 2026-03-26 20:27:25 2026-03_rel