GICD_CLRSPI_NSR Clear Non-secure SPI Pending Register GIC Distributor Dist_base 0x0048 GICD_CLRSPI_NSR WO Removes the pending state from a valid SPI if permitted by the Security state of the access and the GICD_NSACR<n> value for that SPI. A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active. GICD If GICD_TYPER.MBIS == 0, this register is reserved. When GICD_CTLR.DS == 1, this register provides functionality for all SPIs. GICD_CLRSPI_NSR is a 32-bit register. 31 13 31:13 Reserved, RES0. INTID 12 0 12:0 The INTID of the SPI. The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt: For an edge-triggered interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will stop being pending on activation, or if the pending state is removed by a write to GICD_CLRSPI_NSR, GICD_CLRSPI_SR, or GICD_ICPENDR<n>. For a level-sensitive interrupt, a write to GICD_SETSPI_NSR or GICD_SETSPI_SR adds the pending state to the targeted interrupt. It will remain pending until it is deasserted by a write to GICD_CLRSPI_NSR or GICD_CLRSPI_SR. If the interrupt is activated between having the pending state added and being deactivated, then the interrupt will be active and pending. Writes to this register have no effect if: The value written specifies a Secure SPI, the value is written by a Non-secure access, and the value of the corresponding GICD_NSACR<n> register is less than 0b10. The value written specifies an invalid SPI. The SPI is not pending. 16-bit accesses to bits [15:0] of this register must be supported. A Secure access to this register can clear the pending state of any valid SPI. 2026-03-26 20:27:25 2026-03_rel