GICD_CTLR Distributor Control Register GIC Distributor Dist_base 0x0000 GICD_CTLR RW Enables interrupts and affinity routing. GICD The format of this register depends on the Security state of the access and the number of Security states supported, which is specified by GICD_CTLR.DS. GICD_CTLR is a 32-bit register. When access is Secure, in a system that supports two Security states access is Secure, in a system that supports two Security states RWP 31 31 31 Register Write Pending. Read only. Indicates whether a register write is in progress or not: This field tracks writes to: GICD_CTLR[2:0], the Group Enables, for transitions from 1 to 0 only. GICD_CTLR[7:4], the ARE bits, E1NWF bit and DS bit. GICD_ICENABLER<n>. Updates to other register fields are not tracked by this field. 0b0 No register write in progress. The effects of previous register writes to the affected register fields are visible to all logical components of the GIC architecture, including the CPU interfaces. 0b1 Register write in progress. The effects of previous register writes to the affected register fields are not guaranteed to be visible to all logical components of the GIC architecture, including the CPU interfaces, as the effects of the changes are still being propagated. AU 30 8 30:8 Reserved, RES0. E1NWF 7 7 7 Enable 1 of N Wakeup Functionality. It is IMPLEMENTATION DEFINED whether this bit is programmable, or RAZ/WI. If it is implemented, then it has the following behavior: 0b0 A PE that is asleep cannot be picked for 1 of N interrupts. 0b1 A PE that is asleep can be picked for 1 of N interrupts as determined by IMPLEMENTATION DEFINED controls. AU DS 6 6 6 Disable Security. If DS is written from 0 to 1 when GICD_CTLR.ARE_S == 1, then GICD_CTLR.ARE for the single Security state is RAO/WI. If the Distributor only supports a single Security state, this bit is RAO/WI. If the Distributor supports two Security states, it IMPLEMENTATION DEFINED whether this bit is programmable or implemented as RAZ/WI. When this field is set to 1, all accesses to GICD_CTLR access the single Security state view, and all bits are accessible. When set to 1, this field can only be cleared by a hardware reset. Writing this bit from 0 to 1 is UNPREDICTABLE if any of the following is true: GICD_CTLR.EnableGrp0==1. GICD_CTLR.EnableGrp1S==1. GICD_CTLR.EnableGrp1NS==1. One or more INTID is in the Active or Active and Pending state. 0b0 Non-secure accesses are not permitted to access and modify registers that control Group 0 interrupts. 0b1 Non-secure accesses are permitted to access and modify registers that control Group 0 interrupts. '0' ARE_NS 5 5 5 Affinity Routing Enable, Non-secure state. When affinity routing is enabled for the Secure state, this field is RAO/WI. Changing the ARE_NS settings from 0 to 1 is UNPREDICTABLE except when GICD_CTLR.EnableGrp1 Non-secure == 0. Changing the ARE_NS settings from 1 to 0 is UNPREDICTABLE. If GICv2 backward compatibility for Non-secure state is not implemented, this field is RAO/WI. 0b0 Affinity routing disabled for Non-secure state. 0b1 Affinity routing enabled for Non-secure state. '0' ARE_S 4 4 4 Affinity Routing Enable, Secure state. Changing the ARE_S setting from 0 to 1 is UNPREDICTABLE except when all of the following apply: GICD_CTLR.EnableGrp0==0. GICD_CTLR.EnableGrp1S==0. GICD_CTLR.EnableGrp1NS==0. Changing the ARE_S settings from 1 to 0 is UNPREDICTABLE. If GICv2 backward compatibility for Secure state is not implemented, this field is RAO/WI. 0b0 Affinity routing disabled for Secure state. 0b1 Affinity routing enabled for Secure state. '0' 3 3 3 Reserved, RES0. EnableGrp1S 2 2 2 Enable Secure Group 1 interrupts. If GICD_CTLR.ARE_S == 0, this field is RES0. 0b0 Secure Group 1 interrupts are disabled. 0b1 Secure Group 1 interrupts are enabled. AU EnableGrp1NS 1 1 1 Enable Non-secure Group 1 interrupts. This field also controls whether LPIs are forwarded to the PE. 0b0 Non-secure Group 1 interrupts are disabled. 0b1 Non-secure Group 1 interrupts are enabled. AU EnableGrp0 0 0 0 Enable Group 0 interrupts. 0b0 Group 0 interrupts are disabled. 0b1 Group 0 interrupts are enabled. AU When access is Non-secure, in a system that supports two Security states access is Non-secure, in a system that supports two Security states RWP 31 31 31 This bit is a read-only alias of the Secure GICD_CTLR.RWP bit. 30 5 30:5 Reserved, RES0. ARE_NS 4 4 4 This bit is a read/write alias of the Secure GICD_CTLR.ARE_NS bit. If GICv2 backward compatibility for Non-secure state is not implemented, this field is RAO/WI. 3 2 3:2 Reserved, RES0. EnableGrp1A 1 1 1 If ARE_NS == 1, then this bit is a read/write alias of the Secure GICD_CTLR.EnableGrp1NS bit. If ARE_NS == 0, then this bit is RES0. EnableGrp1 0 0 0 If ARE_NS == 0, then this bit is a read/write alias of the Secure GICD_CTLR.EnableGrp1NS bit. If ARE_NS == 1, then this bit is RES0. When in a system that supports only a single Security state in a system that supports only a single Security state RWP 31 31 31 Register Write Pending. Read only. Indicates whether a register write is in progress or not: This field tracks updates to: GICD_CTLR[2:0], the Group Enables, for transitions from 1 to 0 only. GICD_CTLR[7:4], the ARE bits, E1NWF bit and DS bit. GICD_ICENABLER<n>, the bits that allow disabling of SPIs. Updates to other register fields are not tracked by this field. 0b0 No register write in progress. The effects of previous register writes to the affected register fields are visible to all logical components of the GIC architecture, including the CPU interfaces. 0b1 Register write in progress. The effects of previous register writes to the affected register fields are not guaranteed to be visible to all logical components of the GIC architecture, including the CPU interfaces, as the effects of the changes are still being propagated. AU 30 9 30:9 Reserved, RES0. nASSGIreq 8 8 0 Controls whether SGIs have an active state. This bit is WI when any of GICD_CTLR.{EnableGrp0,EnableGrp1} is 1. 0b0 SGIs have an active state and must be deactivated. 0b1 SGIs do not have an active state and do not require deactivation. '0' When GICD_TYPER2.nASSGIcap == '1' 8 8 8 Reserved, RES0. Otherwise E1NWF 7 7 7 Enable 1 of N Wakeup Functionality. It is IMPLEMENTATION DEFINED whether this bit is programmable, or RAZ/WI. If it is implemented, then it has the following behavior: 0b0 A PE that is asleep cannot be picked for 1 of N interrupts. 0b1 A PE that is asleep can be picked for 1 of N interrupts as determined by IMPLEMENTATION DEFINED controls. AU DS 6 6 6 Disable Security. This field is RAO/WI. 5 5 5 Reserved, RES0. ARE 4 4 4 Affinity Routing Enable. Changing the ARE settings from 0 to 1 is UNPREDICTABLE except when all of the following apply: GICD_CTLR.EnableGrp1==0. GICD_CTLR.EnableGrp0==0. Changing ARE from 1 to 0 is UNPREDICTABLE. If GICv2 backward compatibility is not implemented, this field is RAO/WI. 0b0 Affinity routing disabled. 0b1 Affinity routing enabled. '0' 3 2 3:2 Reserved, RES0. EnableGrp1 1 1 1 Enable Group 1 interrupts. 0b0 Group 1 interrupts disabled. 0b1 Group 1 interrupts enabled. AU EnableGrp0 0 0 0 Enable Group 0 interrupts. 0b0 Group 0 interrupts are disabled. 0b1 Group 0 interrupts are enabled. AU When access is Secure, in a system that supports two Security states When access is Non-secure, in a system that supports two Security states When in a system that supports only a single Security state If an interrupt is pending within a CPU interface when the corresponding GICD_CTLR.EnableGrpX bit is written from 1 to 0 the interrupt must be retrieved from the CPU interface. This might have no effect on the forwarded interrupt if it has already been activated. When a write changes the value of ARE for a Security state or the value of the DS bit, the format used for interpreting the remaining bits provided in the write data is the format that applied before the write takes effect. 2026-03-26 20:27:25 2026-03_rel