GICD_ICFGR<n> Interrupt Configuration Registers 0 63 GIC Distributor Dist_base 0x0C00 + (4 * n) GICD_ICFGR<n> RW Determines whether the corresponding interrupt is edge-triggered or level-sensitive. GICD These registers are available in all GIC configurations. If the GIC implementation supports two Security states, these registers are Common. GICD_ICFGR1 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8. Accessing GICD_ICFGR1 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE: Register is RAZ/WI. An UNKNOWN banked copy of the register is accessed. For SGIs and PPIs: When ARE is 1 for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICR_ICFGR<n> For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field. For SGIs, Int_config fields are RO, meaning that GICD_ICFGR0 is RO. Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE. Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state. Fields corresponding to unimplemented interrupts are RAZ/WI. GICD_ICFGR<n> is a 32-bit register. Int_config<x> 31 0 31:0 Indicates whether the interrupt is level-sensitive or edge-triggered. Int_config[0] (bit [2x]) is RES0. For SGIs, this field always indicates edge-triggered. 15 0 0b00 Corresponding interrupt is level-sensitive. 0b10 Corresponding interrupt is edge-triggered. AU For SPIs and PPIs, when GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. 2026-03-26 20:27:25 2026-03_rel