GICD_ICPENDR<n> Interrupt Clear-Pending Registers 0 31 GIC Distributor Dist_base 0x0280 + (4 * n) GICD_ICPENDR<n> RW Removes the pending state from the corresponding interrupt. GICD These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common. The number of implemented GICD_ICPENDR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0. GICD_ICPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8. Accessing GICD_ICPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE: Register is RAZ/WI. An UNKNOWN banked copy of the register is accessed. GICD_ICPENDR<n> is a 32-bit register. Clear_pending_bit<x> 31 0 31:0 For SPIs and PPIs, removes the pending state from interrupt number 32n + x. Reads and writes have the following behavior: 31 0 0b0 If read, indicates that the corresponding interrupt is not pending on any PE. If written, has no effect. 0b1 If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases: If the interrupt is an SGI. In this case, the write is ignored. The pending state of an SGI can be cleared using GICD_CPENDSGIR<n>. If the interrupt is not pending and is not active and pending. If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending. 0x00000000 For INTID m, when DIV and MOD are the integer division and modulo operations: The corresponding GICD_ICPENDR<n> number, n, is given by n = m DIV 32. The offset of the required GICD_ICPENDR is (0x200 + (4*n)). The bit number of the required group modifier bit in this register is m MOD 32. Clear-pending bits for SGIs are RO/WI. When affinity routing is enabled for the Security state of an interrupt: Bits corresponding to SGIs and PPIs are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ICPENDR0. Bits corresponding to Group 0 and Group 1 Secure interrupts can only be cleared by Secure accesses. Bits corresponding to unimplemented interrupts are RAZ/WI. If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses. 2026-03-26 20:27:25 2026-03_rel