GICD_IGRPMODR<n>
Interrupt Group Modifier Registers
0
31
GIC Distributor
Dist_base
0x0D00 + (4 * n)
GICD_IGRPMODR<n>
RW
When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n> registers, controls whether the corresponding interrupt is in:
Secure Group 0.
Non-secure Group 1.
Secure Group 1.
GICD
When GICD_CTLR.DS==0, these registers are Secure.
The number of implemented GICD_IGROUPR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
When GICD_CTLR.ARE_S==0 or GICD_CTLR.DS==1, the GICD_IGRPMODR<n> registers are RES0. An implementation can make these registers RAZ/WI in this case.
GICD_IGRPMODR<n> is a 32-bit register.
Group_modifier_bit<x>
31
0
31:0
Group modifier bit. When affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n> to form a 2-bit field that defines an interrupt group:
Group modifier bitGroup status bitDefinitionShort name
0b00b0Secure Group 0G0S
0b00b1Non-secure Group 1G1NS
0b10b0Secure Group 1G1S
0b10b1Reserved, treated as Non-secure Group 1-
31
0
0x00000000
For INTID m, when DIV and MOD are the integer division and modulo operations:
The corresponding GICD_IGRPMODR<n> number, n, is given by n = m DIV 32.
The offset of the required GICD_IGRPMODR is (0x080 + (4*n)).
The bit number of the required group modifier bit in this register is m MOD 32.
See GICD_IGROUPR<n> for information about the GICD_IGRPMODR0 reset value.
When affinity routing is enabled for Secure state, GICD_IGRPMODR0 is RES0 and equivalent functionality is proved by GICR_IGRPMODR0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
2026-03-26 20:27:25
2026-03_rel