GICD_IGRPMODR<n>E
Interrupt Group Modifier Registers (extended SPI range)
when GICv3.1 is implemented
0
31
GIC Distributor
Dist_base
0x3400 + (4 * n)
GICD_IGRPMODR<n>E
RW
When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:
Secure Group 0.
Non-secure Group 1.
When System register access is enabled, Secure Group 1.
GICD
GICD_IGRPMODR<n>E resets to 0x00000000.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1:
The number of implemented GICD_IGRPMODR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
When GICD_CTLR.DS==0, this register is Secure.
GICD_IGRPMODR<n>E is a 32-bit register.
Group_modifier_bit<x>
31
0
31:0
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:
Group modifier bitGroup status bitDefinitionShort name
0b00b0Secure Group 0G0S
0b00b1Non-secure Group 1G1NS
0b10b0Secure Group 1G1S
0b10b1Reserved, treated as Non-secure Group 1-
31
0
0x00000000
For INTID m, when DIV and MOD are the integer division and modulo operations:
The corresponding GICD_IGRPMODR<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_IGRPMODR<n>E is (0x3400 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGRPMODR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
2026-03-26 20:27:25
2026-03_rel