GICD_INMIR<n> Non-maskable Interrupt Registers, x = 0 to 31 when GICD_TYPER.NMI == '1' 0 31 GIC Distributor Dist_base 0x0F80 + (4 * n) GICD_INMIR<n> RW Holds whether the corresponding SPI has the non-maskable property. GICD The number of implemented GICD_INMIR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0. GICD_INMIR<n> is a 32-bit register. NMI<x> 31 0 31:0 Non-maskable property. This bit is RES0 when the corresponding interrupt is configured as Group 0. 31 0 0b0 Interrupt does not have the non-maskable property. 0b1 Interrupt has the non-maskable property. 0x00000000 For INTID m, when DIV and MOD are the integer division and modulo operations: The corresponding GICD_INMI<n> number, n, is given by n = (m DIV 32). The offset of the required GICD_INMI is (0xF80 + (4*n)). The bit number of the required in this register is (m MOD 32). For SGIs and PPIs: The field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICR_INMIR0. When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0. Bits corresponding to unimplemented interrupts are RAZ/WI. When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel