GICD_INMIR<n>E Non-maskable Interrupt Registers for Extended SPIs, x = 0 to 31 when GICv3.1 is implemented and GICD_TYPER.NMI == '1' 0 31 GIC Distributor Dist_base 0x3B00 + (4 * n) GICD_INMIR<n>E RW Holds whether the corresponding SPI in the extended SPI range has the non-maskable property. GICD When GICD_TYPER.ESPI is 0, these registers are RES0. When GICD_TYPER.ESPI is 1: the number of implemented GICD_INMIR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0. GICD_INMIR<n>E is a 32-bit register. NMI<x> 31 0 31:0 Non-maskable property. If affinity routing is disabled for the Security state of an interrupt, the bit is RES0. This bit is RES0 when the corresponding interrupt is configured as Group 0. 31 0 0b0 Interrupt does not have the non-maskable property. 0b1 Interrupt has the non-maskable property. 0x00000000 For INTID m, when DIV and MOD are the integer division and modulo operations: The corresponding GICD_INMIR<n>E number, n, is given by n = ((m-4096) DIV 32). The offset of the required GICD_INMIR<n>E is (0x3B00 + (4*n)). The bit number in this register is ((m-4096) MOD 32). When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0. Bits corresponding to unimplemented interrupts are RAZ/WI. When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel