GICD_IROUTER<n> Interrupt Routing Registers 32 1019 GIC Distributor Dist_base 0x6000 + (8 * n) GICD_IROUTER<n> RW When affinity routing is enabled, provides routing information for the SPI with INTID n. GICD These registers are available in all configurations of the GIC. If the GIC implementation supports two Security states, these registers are Common. The maximum value of n is given by (32*(GICD_TYPER.ITLinesNumber+1) - 1). GICD_IROUTER<n> registers where n=0 to 31 are reserved. GICD_IROUTER<n> is a 64-bit register. 63 40 63:40 Reserved, RES0. Aff3 39 32 39:32 Affinity level 3. AU Interrupt_Routing_Mode 31 31 31 Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy: If GICD_IROUTER<n>.IRM == 0 and the affinity path does not correspond to an implemented PE, then if the corresponding interrupt becomes pending behavior is CONSTRAINED UNPREDICTABLE: The interrupt is not forwarded to any PE, direct reads return the written value The affinity path is treated as an UNKNOWN implemented PE, direct reads return the UNKNOWN implemented PE The affinity path is treated as an UNKNOWN implemented PE, direct reads return the written value When GICD_TYPER.No1N is 1, 1 of N distribution is not supported. Setting this field to 1 is CONSTRAINED UNPREDICTABLE, the permitted behaviors are: The field behaves as if set to 0 for all purposes. The field behaves as if set to 0 for all purposes other than a direct-read of the register. The interrupt is treated as not targeting any PE. When this bit is set to 1, GICD_IROUTER<n>.{Aff3, Aff2, Aff1, Aff0} are UNKNOWN. An implementation might choose to make the Aff<n> fields RO when this field is 1. 0b0 Interrupts routed to the PE specified by a.b.c.d. In this routing, a, b, c, and d are the values of fields Aff3, Aff2, Aff1, and Aff0 respectively. 0b1 Interrupts routed to any PE defined as a participating node. AU 30 24 30:24 Reserved, RES0. Aff2 23 16 23:16 Affinity level 2. AU Aff1 15 8 15:8 Affinity level 1. AU Aff0 7 0 7:0 Affinity level 0. AU For an SPI with INTID m: The corresponding GICD_IROUTER<n> register number, n, is given by n = m. The offset of the GICD_IROUTER<n> register is 0x6000 + 8n. These registers are used only when affinity routing is enabled. When affinity routing is not enabled: These registers are RES0. An implementation is permitted to make the register RAZ/WI in this case. The GICD_ITARGETSR<n> registers provide interrupt routing information. When affinity routing becomes enabled for a Security state (for example, following a reset or following a write to GICD_CTLR) the value of all writable fields in this register is UNKNOWN for that Security state. When the group of an interrupt changes so the ARE setting for the interrupt changes to 1, the value of this register is UNKNOWN for that interrupt. If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any GICD_IROUTER<n> registers that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses. For each interrupt, a GIC implementation might support fewer than 256 values for an affinity level. In this case, some bits of the corresponding affinity level field might be RO. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel