GICD_IROUTER<n>E Interrupt Routing Registers (Extended SPI Range) when GICv3.1 is implemented 0 1023 GIC Distributor Dist_base 0x8000 + (8 * n) GICD_IROUTER<n>E RW When affinity routing is enabled, provides routing information for the corresponding SPI in the extended SPI range. GICD When GICD_TYPER.ESPI==0, these registers are RES0. When GICD_TYPER.ESPI==1, the number of implemented GICD_IROUTER<n>E registers is (((GICD_TYPER.ESPI_range+1)*32)-1). Registers are numbered from 0. GICD_IROUTER<n>E is a 64-bit register. 63 40 63:40 Reserved, RES0. Aff3 39 32 39:32 Affinity level 3. AU Interrupt_Routing_Mode 31 31 31 Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy: If GICD_IROUTER<n>E.IRM == 0 and the affinity path does not correspond to an implemented PE, then if the corresponding interrupt becomes pending behavior is CONSTRAINED UNPREDICTABLE: The interrupt is not forwarded to any PE, direct reads return the written value The affinity path is treated as an UNKNOWN implemented PE, direct reads return the UNKNOWN implemented PE The affinity path is treated as an UNKNOWN implemented PE, direct reads return the written value When GICD_TYPER.No1N is 1, 1 of N distribution is not supported. Setting this field to 1 is CONSTRAINED UNPREDICTABLE, the permitted behaviors are: The field behaves as if set to 0 for all purposes. The field behaves as if set to 0 for all purposes other than a direct-read of the register. The interrupt is treated as not targeting any PE. When this bit is set to 1, GICD_IROUTER<n>E.{Aff3, Aff2, Aff1, Aff0} are UNKNOWN. An implementation might choose to make the Aff<n> fields RO when this field is 1. 0b0 Interrupts routed to the PE specified by a.b.c.d. In this routing, a, b, c, and d are the values of fields Aff3, Aff2, Aff1, and Aff0 respectively. 0b1 Interrupts routed to any PE defined as a participating node. AU 30 24 30:24 Reserved, RES0. Aff2 23 16 23:16 Affinity level 2. AU Aff1 15 8 15:8 Affinity level 1. AU Aff0 7 0 7:0 Affinity level 0. AU For an SPI with INTID m: The corresponding GICD_IROUTER<n>E register number, n, is given by n = m. The offset of the GICD_IROUTER<n>E register is 0x6000 + 8n. When affinity routing is not enabled for the Security state of an interrupt in GICD_IROUTER<n>E, the register is RES0. When GICD_CTLR.DS==0, a register that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. Bits corresponding to unimplemented interrupts are RAZ/WI. 2026-03-26 20:27:25 2026-03_rel