GICH_APR<n> Active Priorities Registers when FEAT_GICv3_LEGACY is implemented and EL2 is implemented 0 3 GIC Virtual interface control 0x00F0 + (4 * n) GICH_APR<n> When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW These registers track which preemption levels are active in the virtual CPU interface, and indicate the current active priority. Corresponding bits are set to 1 in this register when an interrupt is acknowledged, based on GICH_LR<n>.Priority, and the least significant bit set is cleared on EOI. GICH This register is available when the GIC implementation supports interrupt virtualization. The number of registers required depends on how many bits are implemented in GICH_LR<n>.Priority: When 5 priority bits are implemented, 1 register is required (GICH_APR0). When 6 priority bits are implemented, 2 registers are required (GICH_APR0, GICH_APR1). When 7 priority bits are implemented, 4 registers are required (GICH_APR0, GICH_APR1, GICH_APR2, GICH_APR3). Unimplemented registers are RAZ/WI. GICH_APR<n> is a 32-bit register. P<x> 31 0 31:0 Active priorities. Possible values of each bit are: The correspondence between priorities and bits depends on the number of bits of priority that are implemented. If 5 bits of priority are implemented (bits [7:3] of priority), then there are 32 priority groups, and the active state of these priorities are held in GICH_APR0 in the bits corresponding to Priority[7:3]. If 6 bits of priority are implemented (bits [7:2] of priority), then there are 64 priority groups, and: The active state of priorities 0 - 124 are held in GICH_APR0 in the bits corresponding to 0:Priority[6:2]. The active state of priorities 128 - 252 are held in GICH_APR1 in the bits corresponding to 1:Priority[6:2]. If 7 bits of priority are implemented (bits [7:1] of priority), then there are 128 priority groups, and: The active state of priorities 0 - 62 are held in GICH_APR0 in the bits corresponding to 00:Priority[5:1]. The active state of priorities 64 - 126 are held in GICH_APR1 in the bits corresponding to 01:Priority[5:1]. The active state of priorities 128 - 190 are held in GICH_APR2 in the bits corresponding to 10:Priority[5:1]. The active state of priorities 192 - 254 are held in GICH_APR3 in the bits corresponding to 11:Priority[5:1]. 31 0 0b0 There is no interrupt active at the priority corresponding to that bit. 0b1 There is an interrupt active at the priority corresponding to that bit. 0x00000000 These registers are used only when System register access is not enabled. When System register access is enabled the following registers provide equivalent functionality: In AArch64: For Group 0, ICH_AP0R<n>_EL2. For Group 1, ICH_AP1R<n>_EL2. In AArch32: For Group 0, ICH_AP0R<n>. For Group 1, ICH_AP1R<n>. 2026-03-26 20:27:25 2026-03_rel