GICH_ELRSR Empty List Register Status Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual interface control 0x0030 GICH_ELRSR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO Indicates which List registers contain valid interrupts. GICH This register is available when the GIC implementation supports interrupt virtualization. GICH_ELRSR is a 32-bit register. 31 16 31:16 Reserved, RES0. Status<n> 15 0 15:0 Status bit for List register <n>: For any GICH_LR<n> register, the corresponding status bit is set to 1 if GICH_LR<n>.State is 0b00 and either: GICH_LR<n>.HW == 1. GICH_LR<n>.EOI == 0. 15 0 0b0 GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt. 0b1 GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt. 0x0001 This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICH_ELRSR provides equivalent functionality. For AArch64 implementations, ICH_ELRSR_EL2 provides equivalent functionality. Bits corresponding to unimplemented List registers are RES0. 2026-03-26 20:27:25 2026-03_rel