GICH_HCR Hypervisor Control Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual interface control 0x0000 GICH_HCR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Controls the virtual CPU interface. GICH This register is available when the GIC implementation supports interrupt virtualization. GICH_HCR is a 32-bit register. EOICount 31 27 31:27 Counts the number of EOIs received that do not have a corresponding entry in the List registers. The virtual CPU interface increments this field automatically when a matching EOI is received. EOIs that do not clear a bit in GICH_APR<n> do not cause an increment. If an EOI occurs when the value of this field is 31, then the field wraps to 0. The maintenance interrupt is asserted whenever this field is nonzero and GICH_HCR.LRENPIE == 1. AU 26 8 26:8 Reserved, RES0. VGrp1DIE 7 7 7 VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected virtual machine is disabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when GICV_CTLR.EnableGrp1 == 0. AU VGrp1EIE 6 6 6 VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected virtual machine is enabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when GICV_CTLR.EnableGrp1 == 1. AU VGrp0DIE 5 5 5 VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected virtual machine is disabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when GICV_CTLR.EnableGrp0 == 0. AU VGrp0EIE 4 4 4 VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected virtual machine is enabled: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled when GICV_CTLR.EnableGrp0 == 1. AU NPIE 3 3 3 No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt while no pending interrupts are present in the List registers: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled while the List registers contain no interrupts in the pending state. AU LRENPIE 2 2 2 List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register for an EOI request: 0b0 Maintenance interrupt disabled. 0b1 Maintenance interrupt signaled while GICH_HCR.EOICount is not 0. AU UIE 1 1 1 Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are either empty or hold only one valid entry. 0b0 Maintenance interrupt disabled. 0b1 A maintenance interrupt is signaled if zero or one of the List register entries are marked as a valid interrupt. AU En 0 0 0 Enable. Global enable bit for the virtual CPU interface. When this field is 0: The virtual CPU interface does not signal any maintenance interrupts. The virtual CPU interface does not signal any virtual interrupts. A read of GICV_IAR or GICV_AIAR returns a spurious interrupt ID. 0b0 Virtual CPU interface operation is disabled. 0b1 Virtual CPU interface operation is enabled. AU The VGrp1DIE, VGrp1EIE, VGrp0DIE, and VGrp0EIE fields permit the hypervisor to track the virtual CPU interfaces that are enabled. The hypervisor can then route interrupts that have multiple targets correctly and efficiently, without having to read the virtual CPU interface status. See 'Maintenance interrupts' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069) and GICH_MISR for more information. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICH_HCR provides equivalent functionality. For AArch64 implementations, ICH_HCR_EL2 provides equivalent functionality. GICH_HCR.En must be set to 1 for any virtual or maintenance interrupt to be asserted. 2026-03-26 20:27:25 2026-03_rel