GICH_LR<n> List Registers when FEAT_GICv3_LEGACY is implemented and EL2 is implemented 0 15 GIC Virtual interface control 0x0100 + (4 * n) GICH_LR<n> When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW These registers provide context information for the virtual CPU interface. GICH This register is available when the GIC implementation supports interrupt virtualization. A maximum of 16 List registers can be provided. GICH_VTR.ListRegs defines the number implemented. Unimplemented List registers are RAZ/WI. GICH_LR<n> is a 32-bit register. HW 31 31 31 Indicates whether this virtual interrupt is a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt corresponding to the INTID: 0b0 This interrupt is triggered entirely in software. No notification is sent to the Distributor when the virtual interrupt is deactivated. 0b1 A hardware interrupt. A deactivate interrupt request is sent to the Distributor when the virtual interrupt is deactivated, using GICH_LR<n>.pINTID to indicate the physical interrupt identifier. If GICV_CTLR.EOImode == 0, this request corresponds to a write to GICV_EOIR or GICV_AEOIR, otherwise it corresponds to a write to GICV_DIR. AU Group 30 30 30 Indicates whether the interrupt is Group 0 or Group 1: GICV_CTLR.CBPR controls whether GICV_BPR or GICV_ABPR determines if a pending Group 1 interrupt has sufficient priority to preempt current execution. 0b0 Group 0 virtual interrupt. GICV_CTLR.FIQEn determines whether it is signaled as a virtual IRQ or as a virtual FIQ, and GICV_CTLR.EnableGrp0 enables signaling of this interrupt to the virtual machine. 0b1 Group 1 virtual interrupt, signaled as a virtual IRQ. GICV_CTLR.EnableGrp1 enables signaling of this interrupt to the virtual machine. AU State 29 28 29:28 The state of the interrupt. This field has one of the following values: The GIC updates these state bits as virtual interrupts proceed through the interrupt life cycle. Entries in the inactive state are ignored, except for the purpose of generating virtual maintenance interrupts. For hardware interrupts, the active and pending state is held in the Distributor rather than the virtual CPU interface. A hypervisor must only use the active and pending state for software originated interrupts, which are typically associated with virtual devices, or for SGIs. 0b00 Inactive 0b01 Pending 0b10 Active 0b11 Active and pending AU Priority 27 23 27:23 The priority of this interrupt. AU 22 20 22:20 Reserved, RES0. pINTID 19 10 19:10 The function of this field depends on the value of GICH_LR<n>.HW. When GICH_LR<n>.HW == 0: Bit [19] indicates whether the interrupt triggers an EOI maintenance interrupt. If this bit is 1, then when the interrupt identified by vINTID is deactivated, an EOI maintenance interrupt is asserted. Bits [18:13] are reserved, SBZ. If the vINTID field value corresponds to an SGI (that is, 0-15), bits [12:10] contain the number of the requesting PE. This appears in the corresponding field of GICV_IAR or GICV_AIAR. If the vINTID field value is not 0-15, this field must be cleared to 0. When GICH_LR<n>.HW == 1: This field indicates the pINTID that the hypervisor forwards to the Distributor. This field is only required to implement enough bits to hold a valid value for the ID configuration. Any unused higher order bits are RAZ/WI. If the value of pINTID is 0-15 or 1020-1023, behavior is UNPREDICTABLE. If the value of pINTID is 16-31, this field applies to the PPI associated with this same PE as the virtual CPU interface requesting the deactivation. AU vINTID 9 0 9:0 This INTID is returned to the VM when the interrupt is acknowledged through GICV_IAR. Each valid interrupt stored in the List registers must have a unique vINTID for that virtual CPU interface. If the value of vINTID is 1020-1023, behavior is UNPREDICTABLE. AU This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICH_LR<n> provides equivalent functionality. For AArch64 implementations, ICH_LR<n>_EL2 provides equivalent functionality. 2026-03-26 20:27:25 2026-03_rel