GICH_VMCR Virtual Machine Control Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual interface control 0x0008 GICH_VMCR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Enables the hypervisor to save and restore the virtual machine view of the GIC state. This register is updated when a virtual machine updates the virtual CPU interface registers. GICH This register is available when the GIC implementation supports interrupt virtualization. GICH_VMCR is a 32-bit register. VPMR 31 24 31:24 Virtual priority mask. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE. This alias field is updated when a VM updates GICV_PMR.Priority. AU VBPR0 23 21 23:21 Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 1. This alias field is updated when a VM updates GICV_BPR.Binary_Point. AU VBPR1 20 18 20:18 Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 0. This alias field is updated when a VM updates GICV_ABPR.Binary_Point. AU 17 10 17:10 Reserved, RES0. VEOIM 9 9 9 Virtual EOImode. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.EOImode. 0b0 A write of an INTID to GICV_EOIR or GICV_AEOIR drops the priority of the interrupt with that INTID, and also deactivates that interrupt. 0b1 A write of an INTID to GICV_EOIR or GICV_AEOIR only drops the priority of the interrupt with that INTID. Software must write to GICV_DIR to deactivate the interrupt. AU 8 5 8:5 Reserved, RES0. VCBPR 4 4 4 Virtual Common Binary Point Register. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.CBPR. 0b0 GICV_ABPR determines the preemption group for Group 1 interrupts. 0b1 GICV_BPR determines the preemption group for Group 1 interrupts. AU VFIQEn 3 3 3 Virtual FIQ enable. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.FIQEn. 0b0 Group 0 virtual interrupts are presented as virtual IRQs. 0b1 Group 0 virtual interrupts are presented as virtual FIQs. AU VAckCtl 2 2 2 Virtual AckCtl. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.AckCtl. This field is supported for backward compatibility with GICv2. Arm deprecates the use of this field. 0b0 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022. 0b1 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt. AU VENG1 1 1 1 Virtual interrupt enable, Group 1. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.EnableGrp1. 0b0 Group 1 virtual interrupts are disabled. 0b1 Group 1 virtual interrupts are enabled. AU VENG0 0 0 0 Virtual interrupt enable, Group 0. Possible values of this bit are: This alias field is updated when a VM updates GICV_CTLR.EnableGrp0. 0b0 Group 0 virtual interrupts are disabled. 0b1 Group 0 virtual interrupts are enabled. AU A List register is in the pending state only if the corresponding GICH_LR<n> value is 0b01, that is, pending. The active and pending state is not included. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICH_VMCR provides equivalent functionality. For AArch64 implementations, ICH_VMCR_EL2 provides equivalent functionality. 2026-03-26 20:27:25 2026-03_rel