GICH_VTR Virtual Type Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual interface control 0x0004 GICH_VTR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO Indicates the number of implemented virtual priority bits and List registers. GICH This register is available when the GIC implementation supports interrupt virtualization. GICH_VTR is a 32-bit register. PRIbits 31 29 31:29 The number of virtual priority bits implemented, minus one. An implementation must implement at least 32 levels of virtual priority (5 priority bits). PREbits 28 26 28:26 The number of virtual preemption bits implemented, minus one. An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits). The value of this field must be less than or equal to the value of GICH_VTR.PRIbits. IDbits 25 23 25:23 The number of virtual interrupt identifier bits supported: All other values are reserved. 0b000 16 bits. 0b001 24 bits. SEIS 22 22 22 SEI support. Indicates whether the virtual CPU interface supports generation of SEIs: 0b0 The virtual CPU interface logic does not support generation of SEIs. 0b1 The virtual CPU interface logic supports generation of SEIs. A3V 21 21 21 Affinity 3 valid. Possible values are: 0b0 The virtual CPU interface logic only supports zero values of the Aff3 field in ICC_SGI0R_EL1, ICC_SGI1R_EL1, and ICC_ASGI1R_EL1. 0b1 The virtual CPU interface logic supports nonzero values of the Aff3 field in ICC_SGI0R_EL1, ICC_SGI1R_EL1, and ICC_ASGI1R_EL1. 20 5 20:5 Reserved, RES0. ListRegs 4 0 4:0 The number of implemented List registers, minus one. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICH_VTR provides equivalent functionality. For AArch64 implementations, ICH_VTR_EL2 provides equivalent functionality. 2026-03-26 20:27:25 2026-03_rel