GICR_CTLR
Redistributor Control Register
GIC Redistributor
RD_base
0x0000
GICR_CTLR
RW
Controls the operation of a Redistributor, and enables the signaling of LPIs by the Redistributor to the connected PE.
GICR
A copy of this register is provided for each Redistributor.
GICR_CTLR is a 32-bit register.
UWP
31
31
31
Upstream Write Pending. Read-only. Indicates whether all upstream writes have been communicated to the Distributor.
0b0
The effects of all upstream writes have been communicated to the Distributor, including any Generate SGI packets. For more information, see 'Generate SGI (ICC)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
0b1
Not all the effects of upstream writes, including any Generate SGI packets, have been communicated to the Distributor. For more information, see 'Generate SGI (ICC)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
30
27
30:27
Reserved, RES0.
DPG1S
26
26
26
Disable Processor selection for Group 1 Secure interrupts. When GICR_TYPER.DPGS == 1:
When GICR_TYPER.DPGS == 0 this bit is RAZ/WI.
When GICD_CTLR.DS==1, this field is RAZ/WI. In GIC implementations that support two Security states, this field is only accessible by Secure accesses, and is RAZ/WI to Non-secure accesses.
It is IMPLEMENTATION DEFINED whether these bits affect the selection of PEs for interrupts using the 1 of N distribution model when GICD_CTLR.ARE_S==0.
0b0
A Group 1 Secure SPI configured to use the 1 of N distribution model can select this PE, if the PE is not asleep and if Secure Group 1 interrupts are enabled.
0b1
A Group 1 Secure SPI configured to use the 1 of N distribution model cannot select this PE.
'0'
DPG1NS
25
25
25
Disable Processor selection for Group 1 Non-secure interrupts. When GICR_TYPER.DPGS == 1:
When GICR_TYPER.DPGS == 0 this bit is RAZ/WI.
It is IMPLEMENTATION DEFINED whether these bits affect the selection of PEs for interrupts using the 1 of N distribution model when GICD_CTLR.ARE_NS==0.
0b0
A Group 1 Non-secure SPI configured to use the 1 of N distribution model can select this PE, if the PE is not asleep and if Non-secure Group 1 interrupts are enabled.
0b1
A Group 1 Non-secure SPI configured to use the 1 of N distribution model cannot select this PE.
'0'
DPG0
24
24
24
Disable Processor selection for Group 0 interrupts. When GICR_TYPER.DPGS == 1:
When GICR_TYPER.DPGS == 0 this bit is RAZ/WI.
When GICD_CTLR.DS == 1, this field is always accessible. In GIC implementations that support two Security states, this field is RAZ/WI to Non-secure accesses.
It is IMPLEMENTATION DEFINED whether these bits affect the selection of PEs for interrupts using the 1 of N distribution model when GICD_CTLR.ARE_S == 0.
0b0
A Group 0 SPI configured to use the 1 of N distribution model can select this PE, if the PE is not asleep and if Group 0 interrupts are enabled.
0b1
A Group 0 SPI configured to use the 1 of N distribution model cannot select this PE.
'0'
23
4
23:4
Reserved, RES0.
RWP
3
3
3
Register Write Pending. This bit indicates whether a register write for the current Security state is in progress or not.
0b0
The effect of all previous writes to the following registers are visible to all agents in the system:
GICR_ICENABLER0
GICR_CTLR.DPG1S
GICR_CTLR.DPG1NS
GICR_CTLR.DPG0
GICR_CTLR, which clears EnableLPIs from 1 to 0.
In FEAT_GICv4p1, GICR_VPROPBASER, which clears Valid from 1 to 0.
0b1
The effect of all previous writes to the following registers are not guaranteed by the architecture to be visible to all agents in the system while the changes are still being propagated:
GICR_ICENABLER0
GICR_CTLR.DPG1S
GICR_CTLR.DPG1NS
GICR_CTLR.DPG0
GICR_CTLR, which clears EnableLPIs from 1 to 0.
In FEAT_GICv4p1, GICR_VPROPBASER, which clears Valid from 1 to 0.
IR
2
2
2
LPI invalidate registers supported.
This bit is read-only.
If GICR_TYPER.DirectLPI is 1 or GICR_TYPER.RVPEI is 1, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR are always implemented.
Arm recommends that implementations report GICR_CTLR.IR as 1 in these cases.
0b0
This bit does not indicate whether the GICR_INVLPIR, GICR_INVALLR and GICR_SYNCR are implemented or not.
0b1
GICR_INVLPIR, GICR_INVALLR and GICR_SYNCR are implemented.
CES
1
1
1
Clear Enable Supported.
This bit is read-only.
Implementing GICR_CTLR.EnableLPIs as programmable and not reporting GICR_CLTR.CES == 1 is deprecated.
Implementing GICR_CTLR.EnableLPIs as RES1 once set is deprecated.
When GICR_CLTR.CES == 0, software cannot assume that GICR_CTLR.EnableLPIs is programmable without observing the bit being cleared to 0.
0b0
The IRI does not indicate whether GICR_CTLR.EnableLPIs is RES1 once set.
0b1
GICR_CTLR.EnableLPIs is not RES1 once set.
EnableLPIs
0
0
0
In implementations where affinity routing is enabled for the Security state:
If GICR_TYPER.PLPIS == 0, this field is RES0.
If GICD_CTLR.ARE_NS is written from 1 to 0 when this bit is 1, behavior is an IMPLEMENTATION DEFINED choice between clearing GICR_CTLR.EnableLPIs to 0 or maintaining its current value.When affinity routing is not enabled for the Non-secure state, this bit is RES0.
When written from 0 to 1, the Redistributor loads the LPI Pending table from memory to check for any pending interrupts.
After it has been written to 1, it is IMPLEMENTATION DEFINED whether the bit becomes RES1 or can be cleared by to 0.
Where the bit remains programmable:
Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs from 1 to 0 before writing GICR_PENDBASER or GICR_PROPBASER, otherwise behavior is UNPREDICTABLE.
Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs from 1 to 0 before setting GICR_CTLR.EnableLPIs to 1, otherwise behavior is UNPREDICTABLE.
If one or more ITS is implemented, Arm strongly recommends that all LPIs are mapped to another Redistributor before GICR_CTLR.EnableLPIs is cleared to 0.
0b0
LPI support is disabled. Any doorbell interrupt generated as a result of a write to a virtual LPI register must be discarded, and any ITS translation requests or commands involving LPIs in this Redistributor are ignored.
0b1
LPI support is enabled.
'0'
The participation of a PE in the 1 of N distribution model for a given interrupt group is governed by the concatenation of GICR_WAKER.ProcessorSleep, the appropriate GICR_CTLR.DPG{1, 0} bit, and the PE interrupt group enable. The behavior options are:
PSDPG{1S, 1NS, 0}EnablePE Behavior
0b00b00b0The PE cannot be selected.
0b00b00b1The PE can be selected.
0b00b1*The PE cannot be selected.
0b1**The PE cannot be selected when GICD_CTLR.E1NWF == 0. When GICD_CTLR.E1NWF == 1, the mechanism by which PEs are selected is IMPLEMENTATION DEFINED.
If an SPI using the 1 of N distribution model has been forwarded to the PE, and a write to GICR_CTLR occurs that changes the DPG bit for the interrupt group of the SPI, the IRI must attempt to select a different target PE for the SPI. This might have no effect on the forwarded SPI if it has already been activated.
2026-03-26 20:27:25
2026-03_rel