GICR_ICENABLER<n>E Interrupt Clear-Enable Registers when GICv3.1 is implemented 1 2 GIC Redistributor SGI_base 0x0180 + (4 * n) GICR_ICENABLER<n>E RW Disables forwarding of the corresponding PPI to the CPU interfaces. GICR A copy of this register is provided for each Redistributor. GICR_ICENABLER<n>E is a 32-bit register. Clear_enable_bit<x> 31 0 31:0 For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior: 31 0 0b0 If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect. 0b1 If read, indicates that forwarding of the corresponding interrupt is enabled. If written, disables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 0. 0x00000000 For INTID m, when DIV and MOD are the integer division and modulo operations: The corresponding GICR_ICENABLER<n>E number, n, is given by n = (m-1024) DIV 32. The offset of the required GICR_ICENABLER<n>E is (0x180 + (4*n)). The bit number of the required group modifier bit in this register is (m-1024) MOD 32. When affinity routing is not enabled for the Security state of an interrupt in GICR_ICENABLER<n>E, the corresponding bit is RES0. When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses. Bits corresponding to unimplemented interrupts are RAZ/WI. 2026-03-26 20:27:25 2026-03_rel