GICR_ICFGR1 Interrupt Configuration Register 1 GIC Redistributor SGI_base 0x0C04 GICR_ICFGR1 RW Determines whether the corresponding PPI is edge-triggered or level-sensitive. GICR A copy of this register is provided for each Redistributor. For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field. Changing Int_config when the interrupt is individually enabled is UNPREDICTABLE. Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state. GICR_ICFGR1 is a 32-bit register. Int_config<x> 31 0 31:0 Indicates whether the interrupt is level-sensitive or edge-triggered. Int_config[0] (bit [2x]) is RES0. 15 0 0b00 Corresponding interrupt is level-sensitive. 0b10 Corresponding interrupt is edge-triggered. AU This register is used when affinity routing is enabled. When affinity routing is disabled for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICD_ICFGR<n> with n=1. When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. 2026-03-26 20:27:25 2026-03_rel