GICR_ICFGR<n>E Interrupt configuration registers when GICv3.1 is implemented 2 5 GIC Redistributor SGI_base 0x0C00 + (4 * n) GICR_ICFGR<n>E RW Determines whether the corresponding PPI in the extended PPI range is edge-triggered or level-sensitive. GICR A copy of this register is provided for each Redistributor. GICR_ICFGR<n>E is a 32-bit register. Int_config<x> 31 0 31:0 Indicates whether the interrupt is level-sensitive or edge-triggered. Int_config[0] (bit [2x]) is RES0. 15 0 0b00 The corresponding interrupt is level-sensitive. 0b10 The corresponding interrupt is edge-triggered. AU For each supported extended PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field. When affinity routing is not enabled for the Security state of an interrupt in GICR_ICFGR<n>E, the corresponding bit is RES0. When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. Bits corresponding to unimplemented interrupts are RAZ/WI. 2026-03-26 20:27:25 2026-03_rel