GICR_IGROUPR0 Interrupt Group Register 0 GIC Redistributor SGI_base 0x0080 GICR_IGROUPR0 RW Controls whether the corresponding SGI or PPI is in Group 0 or Group 1. GICR This register is available in all GIC configurations. If the GIC implementation supports two Security states, this register is Secure. A copy of this register is provided for each Redistributor. GICR_IGROUPR0 is a 32-bit register. Redistributor_group_status_bit<x> 31 0 31:0 Group status bit. In this register: Bits [31:16] are group status bits for PPIs. Bits [15:0] are group status bits for SGIs. When GICD_CTLR.DS == 0, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGRPMODR0 to form a 2-bit field that defines an interrupt group. The encoding of this field is at GICR_IGRPMODR0. 31 0 0b0 When GICD_CTLR.DS==1, the corresponding interrupt is Group 0. When GICD_CTLR.DS==0, the corresponding interrupt is Secure. 0b1 When GICD_CTLR.DS==1, the corresponding interrupt is Group 1. When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1. AU The considerations for the reset value of this register are the same as those for GICD_IGROUPR<n> with n=0. When affinity routing is not enabled for the Security state of an interrupt in GICR_IGROUPR0, the corresponding bit is RES0 and equivalent functionality is provided by GICD_IGROUPR<n> with n=0. When GICD_CTLR.DS == 0, the register is RAZ/WI to Non-secure accesses. Bits corresponding to unimplemented interrupts are RAZ/WI. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel