GICR_IGRPMODR0
Interrupt Group Modifier Register 0
GIC Redistributor
SGI_base
0x0D00
GICR_IGRPMODR0
RW
When GICD_CTLR.DS==0, this register together with the GICR_IGROUPR0 register, controls whether the corresponding interrupt is in:
Secure Group 0.
Non-secure Group 1.
When System register access is enabled, Secure Group 1.
GICR
When GICD_CTLR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGRPMODR0 is a 32-bit register.
Group_modifier_bit<x>
31
0
31:0
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGROUPR0 to form a 2-bit field that defines an interrupt group:
Group modifier bitGroup status bitDefinitionShort name
0b00b0Secure Group 0G0S
0b00b1Non-secure Group 1G1NS
0b10b0Secure Group 1G1S
0b10b1Reserved, treated as Non-secure Group 1-
31
0
AU
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGRPMODR0, the corresponding bit is RES0 and equivalent functionality is provided by GICD_IGRPMODR<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_IGRPMODR<n>.
When GICD_CTLR.ARE_S == 0 or GICD_CTLR.DS == 1, GICR_IGRPMODR0 is RES0. An implementation can make this register RAZ/WI in this case.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
2026-03-26 20:27:25
2026-03_rel