GICR_INMIR0 Non-maskable Interrupt Register 0 when GICD_TYPER.NMI == '1' GIC Redistributor SGI_base 0x0F80 GICR_INMIR0 RW Controls whether the corresponding SGI or PPI has the non-maskable property. GICR A copy of this register is provided for each Redistributor. GICR_INMIR0 is a 32-bit register. nmi<x> 31 0 31:0 Non-maskable property. 31 0 0b0 Interrupt does not have the non-maskable property. 0b1 Interrupt has the non-maskable property. 0x00000000 If affinity routing is disabled for the Security state of an interrupt, the bit is RES0. This bit is RES0 when the corresponding interrupt is configured as Group 0. Bits corresponding to unimplemented interrupts are RAZ/WI. When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel