<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>GICR_INVLPIR</reg_short_name>
        
        <reg_long_name>Redistributor Invalidate LPI Register</reg_long_name>



      
      

    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>GIC Redistributor</reg_component>
    <reg_frame>RD_base</reg_frame>
    <reg_offset><hexnumber>0x00A0</hexnumber></reg_offset>
    <reg_instance>GICR_INVLPIR</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_type>WO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Invalidates the cached configuration data of a specified LPI, causing the GIC to reload the interrupt configuration from the appropriate LPI Configuration table.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>GICR</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>A copy of this register is provided for each Redistributor.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>GICR_INVLPIR is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_63-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>V</field_name>
    <field_msb>63</field_msb>
    <field_lsb>63</field_lsb>
    <rel_range>0</rel_range>
    <field_description order="before">
      <para>Indicates whether the INTID is virtual or physical.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Invalidate is for a physical INTID.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Invalidate is for a virtual INTID.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <fields_condition>When GICv4.1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-63_63-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>63</field_lsb>
    <rel_range>63</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-62_48" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>62</field_msb>
    <field_lsb>48</field_lsb>
    <rel_range>62:48</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-47_32-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>vPEID</field_name>
    <field_msb>47</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>15:0</rel_range>
    <field_description order="before"><para>When GICR_INVLPIR.V == 0, this field is <arm-defined-word>RES0</arm-defined-word></para>
<para>When GICR_INVLPIR.V == 1, this field is the target vPEID of the invalidate.</para>
<note><para>The size of this field is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>, and is specified by the <register_link state="ext" id="ext-gicd_typer2.xml">GICD_TYPER2</register_link>.VIL and <register_link state="ext" id="ext-gicd_typer2.xml">GICD_TYPER2</register_link>.VID fields. Unimplemented bits are <arm-defined-word>RES0</arm-defined-word>.</para></note></field_description>
    <fields_condition>When GICv4.1 is implemented</fields_condition>
  </field>
  <field id="fieldset_0-47_32-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>47</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>47:32</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>INTID</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before"><para>The INTID of the LPI to be invalidated.</para>
<note><para>The size of this field is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>, and is specified by the <register_link state="ext" id="ext-gicd_typer.xml">GICD_TYPER</register_link>.IDbits field. Unimplemented bits are <arm-defined-word>RES0</arm-defined-word>.</para></note></field_description>
  </field>
  <text_after_fields>
    <note>
      <para>If any LPI has been forwarded to the PE and a valid write to GICR_INVLPIR is received, the Redistributor must ensure it reloads its properties from memory and apply any changes by retrieving and reforwarding the LPI as required. This has no effect on the forwarded LPI if it has already been activated.</para>
    </note>
  </text_after_fields>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_63-1" msb="63" lsb="63"/>
  <fieldat id="fieldset_0-62_48" msb="62" lsb="48"/>
  <fieldat id="fieldset_0-47_32-1" msb="47" lsb="32"/>
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>When written with a 32-bit write the data is zero-extended to 64 bits.</para>

      </access_permission_text>
      <access_permission_text>
        <para>This register is mandatory when any of the following are true:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content><register_link state="ext" id="ext-gicr_typer.xml">GICR_TYPER</register_link>.Direct is 1.</content>
</listitem><listitem><content><register_link state="ext" id="ext-gicr_ctlr.xml">GICR_CTLR</register_link>.IR is 1.</content>
</listitem><listitem><content>GICv4.1 is implemented.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>Otherwise, the functionality is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>

      </access_permission_text>
      <access_permission_text>
        <para>Writes to this register have no effect if either:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>The specified LPI is not currently stored in the local Redistributor.</content>
</listitem><listitem><content>The INTID field corresponds to an unimplemented LPI.</content>
</listitem></list>
      </access_permission_text>





    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>