GICR_IPRIORITYR<n> Interrupt Priority Registers 0 7 GIC Redistributor SGI_base 0x0400 + (4 * n) GICR_IPRIORITYR<n> RW Holds the priority of the corresponding interrupt for each SGI and PPI supported by the GIC. GICR A copy of these registers is provided for each Redistributor. These registers are configured as follows: GICR_IPRIORITYR0-GICR_IPRIORITYR3 store the priority of SGIs. GICR_IPRIORITYR4-GICR_IPRIORITYR7 store the priority of PPIs. GICR_IPRIORITYR<n> is a 32-bit register. Priority_offset_3B 31 24 31:24 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 3. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_2B 23 16 23:16 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 2. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_1B 15 8 15:8 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 1. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_0B 7 0 7:0 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 0. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU These registers are used when affinity routing is enabled for the Security state of the interrupt. When affinity routing is not enabled the bits corresponding to the interrupt are RAZ/WI and GICD_IPRIORITYR<n> provides equivalent functionality. These registers are used for SGIs and PPIs only. Equivalent functionality for SPIs is provided by GICD_IPRIORITYR<n>. These registers are byte-accessible. When GICD_CTLR.DS == 0: A field that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. A Non-secure access to a field that corresponds to a Non-secure Group 1 interrupt behaves as described in 'Software accesses of interrupt priority' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel